Patent US4594685A successfully refreshed from Google Patents.
US4594685A
Expired / Lapsed
US
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Watchdog timer
Assignee: SASIB SpA Bologna
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Filing: 1983-06-24
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Granted: 1986-06-10
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Expires: 2003-06-24
Abstract
Abstract The invention provides apparatus and method to verify appropriate program execution. Hardware external to a processor includes a resettable timer and a shift register for storing and shifting a bit pattern. Internally of the processor a bit pattern is also manipulated by a routine which also outputs a clock signal. A selected bit from each of the patterns is compared on each clock signal. If the clock signal repeats at a sufficiently rapid rate to keep the timer from expiring and, if the comparison is favorable, the processor is allowed to run; otherwise it is reset.
Inventors
- 👤 Jeffrey Owens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:11
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
203 words
Apparatus for tracking appropriate program execution of a digital processor including: program means stored in a memory of said digital processor and including first and second program segment means, said first program segment means including means for accessing a watchdog routine for passing a bit pattern to said watchdog routine and accepting a bit pattern therefrom, said second program segment means comprising said watchdog routine which includes means for (1) outputting a particular bit of said bit pattern passed on said access, (2) manipulating said bit pattern in a predetermined fashion, (3) returning said manipulated bit pattern to said accessing routine and (4) sequentially changing a clocking bit from an initial condition to a different temporary condition and back to said initial condition, and, external to said processor bit pattern means including an input for storing another bit pattern, and including means for: (1) manipulating said another bit pattern in a manner identical to said predetermined fashion, and (2) comparing said outputted particular bit with a selected bit of said stored another bit pattern each time said clocking bit exhibits said sequential changes, and reset means for resetting said processor if said comparison effected by said bit pattern means results in an inequality.
Claim 2
Dependent Claim
203 words
Apparatus for tracking appropriate program execution of a digital processor including: program means stored in a memory of said digital processor and including first and second program segment means, said first program segment means including means for accessing a watchdog routine for passing a bit pattern to said watchdog routine and accepting a bit pattern therefrom, said second program segment means comprising said watchdog routine which includes means for (1) outputting a particular bit of said bit pattern passed on said access, (2) manipulating said bit pattern in a predetermined fashion, (3) returning said manipulated bit pattern to said accessing routine and (4) sequentially changing a clocking bit from an initial condition to a different temporary condition and back to said initial condition, and, external to said processor bit pattern means including an input for storing another bit pattern, and including means for: (1) manipulating said another bit pattern in a manner identical to said predetermined fashion, and (2) comparing said outputted particular bit with a selected bit of said stored another bit pattern each time said clocking bit exhibits said sequential changes, and reset means for resetting said processor if said comparison effected by said bit pattern means results in an inequality.
Claim 3
Dependent Claim
89 words
The apparatus of claim 1 further including a means responsive to said clocking bit for maintaining a timer means in one condition for so long as said clocking bit is sequentially changed at a rate in excess of a threshold and including means for attaining a different condition for said timer means is said another bit fails to exhibit said sequential changes at a rate in excess of said threshold, and wherein said reset means includes means to reset said processor if said timer means attains said different condition.
Claim 4
Dependent Claim
28 words
The apparatus of claim 1 in which said memory of said digital processor includes a different storage location for storing said bit pattern received on each said access.
Claim 5
Dependent Claim
93 words
The apparatus of claim 1 in which said bit pattern means includes: a shift register of length equal to said another bit pattern, means clocking said shift register each time said clocking bit undergoes said sequential changes, means coupling said output of said shift register back to an input of said shift register, an OR gate with one input coupled to an output of said shift register and another input receiving said outputted particular bit, and said reset means includes: means for coupling an output of said OR gate to said digital processor.
Claim 6
Dependent Claim
47 words
The apparatus of claim 4 which further includes: means for timing a predetermined period, means responsive to an expiration of said period for providing an output to said reset means, and means responsive to said sequential changes of said clocking bit for clearing said means for timing.
Claim 7
Independent Claim
251 words
A method of tracking appropriate program execution of a processor including the steps of: a. distributing a plurality of instruction groups within said program whose execution is to be checked, b. each of said instruction groups retrieving a bit pattern from a first predetermined storage location, accessing a watchdog routine for execution thereof, passing the bit pattern retrieved from said predetermined storage location to said watchdog routine, and on return from said watchdog routine, writing a bit pattern received from said watchdog routine to a second predetermined storage location, c. and providing said watchdog routine to effect the functions of: 1. outputting, at a first output location of the processor, a bir from said bit pattern retrieved by said instruction groups, 2. manipulating said bit pattern received by said watchdog routine and passing said manipulated bit pattern on a return from said access, 3. providing a sequential alteration of a clocking bit at a second output location of the processor from an initial condition, to a temporarily different condition, and back to said initial condition, and 4. returning from said access, and external to said processor: d. providing for storage of an external bit pattern, e. manipulating said external bit pattern in a fashion identical to step c(2) each time said second output location undergoes said sequential alteration, f. comparing said output bit at said first output location with a selected bit of said stored external bit pattern, and g. resetting said processor in the event said comparison produces an inequality.
Claim 8
Independent Claim
251 words
A method of tracking appropriate program execution of a processor including the steps of: a. distributing a plurality of instruction groups within said program whose execution is to be checked, b. each of said instruction groups retrieving a bit pattern from a first predetermined storage location, accessing a watchdog routine for execution thereof, passing the bit pattern retrieved from said predetermined storage location to said watchdog routine, and on return from said watchdog routine, writing a bit pattern received from said watchdog routine to a second predetermined storage location, c. and providing said watchdog routine to effect the functions of: 1. outputting, at a first output location of the processor, a bir from said bit pattern retrieved by said instruction groups, 2. manipulating said bit pattern received by said watchdog routine and passing said manipulated bit pattern on a return from said access, 3. providing a sequential alteration of a clocking bit at a second output location of the processor from an initial condition, to a temporarily different condition, and back to said initial condition, and 4. returning from said access, and external to said processor: d. providing for storage of an external bit pattern, e. manipulating said external bit pattern in a fashion identical to step c(2) each time said second output location undergoes said sequential alteration, f. comparing said output bit at said first output location with a selected bit of said stored external bit pattern, and g. resetting said processor in the event said comparison produces an inequality.
Claim 9
Dependent Claim
38 words
The method of claim 6 which further includes the steps of: h. monitoring the period between sequential outputs provided as a result of step c(3) and i. resetting said processor in the event said period exceeds a threshold.
Claim 10
Dependent Claim
119 words
The method of claim 7 in which said monitoring step comprises the step of: 1. providing a counter to count up at a predetermined rate from a zero condition to a terminal condition, and providing a signal when said terminal condition is reached, continuously shifting out the contents of a shift register to provide a clearing signal for said counter, while maintaining a low input on a serial input terminal of said shift register, reloading said shift register with a bit pattern including at least one high bit each time said step c(3) is performed, whereby said counter is cleared prior to reaching its terminal count so long as said shift register is reloaded at an appropriately high rate.
Claim 11
Dependent Claim
26 words
The method of claim 8 in which said shift register is reloaded with the bit pattern which includes a "low" bit in the most significant position.
Claim 12
Dependent Claim
22 words
The method of claim 6 in which said first and second predetermined storage locations are different for each of said instruction groups.
Claim 13
Dependent Claim
24 words
The method of claim 6 wherein all of said first and second predetermined storage locations are distributed through a read/write memory of said processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-09 | 1989-12-09 | 1990-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-09 | 1993-12-09 | 1994-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-09 | 1997-12-09 | 1998-06-10 | $7700.00 | Window Closed / Lapsed |