Character oriented RAM mapping system and method therefor

Claim 2

In a video display system including a raster-scanned video display unit, a video display processor, a digital data memory coupled to said video display processor and responsive to output signals therefrom, said digital data memory including a first plurality of addressable memory locations for generating a first digital X-Y matrix, bit-mapping address signal defined by a plurality of locations each containing a pixel data bit and including m low order bits and n higher order bits representing the column and row coordinates, respectively, of a given location on said video display unit, and a video display unit controller coupling said video display processor and said digital data memory to said video display unit for presenting video information thereon, said video display unit controller having a second plurality of addressable memory locations therein each representing a given location on said video display unit and responsive to a second address signal comprised of x higher order bits representing a given position along a scan line on said video display unit and y lower order bits representing a given scan line on said video display unit, wherein said first and second address signals are represented in binary form to the base A, where A is a multiple of 2 and m+n=X+Y, and one scan line of said video display unit is comprised of A bytes of video information, a method for converting said first address signal to said second address signal for driving said video display unit controller comprising: shifting the m low order bits of said first address signal toward the higher order bits therein y data bit locations; shiiting the y lowest order bits of said n higher order bits of said first address signal toward the lower order bits therein m data bit locations, in generating a first intermediate address signal having (n-y)+(m=y) higher order bits and a plurality of low order bits; converting the higher order bits of said first intermediate address signal to a continuous mapping function in generating a second intermediate address signal, whereby a continuous, 1:1 correlation exists between the respective locations on said video display unit represented by said first and second address signals; and providing said second intermediate address signal to said video display unit controller for presenting video information on said video display unit in terms of said X-Y matrix, bit mapping address signal.

Claim 3

The method of claim 1 wherein said first and second addreqs signals are expressed in hexadecimal binary notation with A=16 and wherein: m=7, n=9, x=12, and y=4.

Claim 4

The method of claim 1 wherein the (n-y)+(m-y) higher order bits of said second intermediate address signal represent the row coordinates and said low order bits thereof represent the column coordinates of a given location on said video display unit.

Claim 5

The method of claim 3 further including adding a predetermined value to the (n-y)+(m-y) higher order bits of said first intermediate address signal during a vertical retrace interval of said video display unit for sequential displacing upward on said video display unit the contents of each scan line thereof, said predetermined value representing the number of scan lines displaced upward during each vertical retrace interval.

Claim 6

The method of claim 4 wherein the contents of the second plurality of addressable locations in said video display unit controller accessed by said second intermediate address signal are not transferred to other addressable locations in said video display unit controller when the contents of each scan line on said video display unit are sequentially displaced upward.

Claim 7

The method of claim 1 wherein said first address signal is adapted for a first mode of operation of said video display system wherein graphics information is displayed on said video display unit and said second address signal is adapted for a second mode of operation of said video display system wherein alphanumeric characters are displayed on said video display unit.

Claim 8

The method of claim 1 wherein the step of converting the higher order bits of said first intermediate address signal includes storing in a data memory having a plurality of addressable locations a plurality of digital data words corresponding to a continuum of values of said second intermediate address signal and selectively reading said digital data words therefrom in response to first intermediate address words provided thereto.

Claim 9

The method of claim 1 wherein the higher order bits of said first and second intermediate address signals represent respective first and second monotonically increasing sequences of address locations wherein said first monotonically increasing sequence is more compact than said second monotonically increasing sequence and said second monotonically increasing sequence is continuous.

Claim 10

In a video display system including a raster-scanned video display unit, a video display processor responsive to user-initiated input commands for generating an output signal in response thereto, a first digital data memory coupled to said video display processor and having stored therein a first plurality of digital code elements in an addressable X-Y array, each of said first plurality of digital code elements representing a particular location on said video display unit for generating in response to said output signal a first X-Y matrix, bit-mapping address signal defined by a plurality of locations each containing a pixel data bit and including m low order bits and n higher order bits representing the column and row coordinates, respectively, of said location on said video display unit, and a video display unit controller coupling said video display processor and said digital data memory to said video display unit for presenting video information thereon, said video display unit controller having a second plurality of digital code elements therein each representing a given location on said video display unit and responsive to a second address signal comprised of x higher order bits representing a given position along a scan line on said video display unit and y lower order bits representing a given scan line on said video display unit, wherein said first and second address signals are represented in binary form to the base A, where A is a multiple of 2 and m+n=X+Y, and one scan line of said video display unit is comprised of A bytes of video information, an address signal bit mapping system comprising: first bit shifting means coupled to said video display processor and said first digital data memory for shifting the m low order bits of said first address signal toward the higher order bits therein y bit locations; second bit shifting means coupled to said video display processor and said first digital data memory for shifting the y lowest order bits of said n higher order bits of said first address signal toward the lower order bits therein m bit locations, in generating a first intermediate address signal having (n-y)+(m-y) higher order bits and a plurality of low order bits; bit mapping conversion means coupling said video display processor and said first digital data memory for converting the higher order bits of said first intermediate address signal to a continuous mapping function in generating a second intermediate address signal, whereby a continuous, 1:1 correlation exists between the respective locations on said video display unit represented by said first and second address signals and providing said second intermediate address signal to said video display unit controller for presenting video information on said video display unit in terms of said X-Y matrix, bit mapping address signal; wherein said bit mapping conversion means includes a read only memory (ROM) having a plurality of addressable locations, each of said addressable locations containing a digital mapping word for generating said continuous mapping function in providing said second intermediate address signal to said video display controller in response to said first address signal provided thereto.

Claim 11

In a video display system including a raster-scanned video display unit, a video display processor responsive to user-initiated input commands for generating an output signal in response thereto, a first digital data memory coupled to said video display processor and having stored therein a first plurality of digital code elements in an addressable X-Y array, each of said first plurality of digital code elements representing a particular location on said video display unit for generating in response to said output signal a first X-Y matrix, bit-mapping address signal defined by a plurality of locations each containing a pixel data bit and including m low order bits and n higher order bits representing the column and row coordinates, respectively, of said location on said video display unit, and a video display unit controller coupling said video display processor and said digital data memory to said video display unit for presenting video information thereon, said video display unit controller having a second plurality of digital code elements therein each representing a given location on said video display unit and responsive to a second address signal comprised of x higher order bits representing a given position along a scan line on said video display unit and y lower order bits representing a given scan line on said video display unit, wherein said first and second address signals are represented in binary form to the base A, where A is a multiple of 2 and m+n=X+Y, and one scan line of said video display unit is comprised of A bytes of video information, an address signal bit mapping system comprising: first bit shifting means coupled to said video display processor and said first digital data memory for shifting the m low order bits of said first address signal toward the higher order bits therein y bit locations; second bit shifting means coupled to said video display processor and said first digital data memory for shifting the y lowest order bits of said n higher order bits of said first address signal toward the lower order bits therein m bit locations, in generating a first intermediate address signal having (n-y)+(m-y) higher order bits and a plurality of low order bits; bit mapping conversion means coupling said video display processor and said first digital data memory for converting the higher order bits of said first intermediate address signal to a continuous mapping function in generating a second intermediate address signal, whereby a continuous, 1:1 correlation exists between the respective locations on said video display unit represented by said first and second address signals and providing said second intermediate address signal to said video display unit controller for presenting video information on said video display unit in terms of said X-Y matrix, bit mapping address signal; wherein said bit mapping conversion means includes a read only memory (ROM) having a plurality of addressable locations, each of said addressable locations containing a digital mapping word for generating said continuous mapping function in providing said second intermediate address signal to said video display controller in response to said first address signal provided thereto.

Claim 12

The system of claim 9 further including adding means coupled to said video display processor and said first digital data memory for adding a predetermined value to the (n-y)+(m-y) high order bits of the bit-shifted first address signal during a vertical retrace interval of said video display unit for sequentially displacing upward on said video display unit the contents of each scan line thereof, wherein said predetermined value is a multiple of the bit length of a single scan line on said video display unit.