Two-level transistor structures and method utilizing minimal area therefor

Claim 1

A method for manufacturing complementary self-aligned NMOS and PMOS stacked transistors using a P doped silicon substrate, comprising the steps of: selectively growing field oxide around an active area on a first surface of the substrate; growing a gate oxide over the active area; depositing a layer of undoped polysilicon over the first surface, followed by recrystallization of the polysilicon; doping the polysilicon N-; delineating an N gate region for the NMOS transistor being formed from the polysilicon layer and an active area from the polysilicon layer on the field oxide for the PMOS transistor being formed; outlining the NMOS active area for the NMOS transistor being formed; ion implanting N+ dopant in the outlined NMOS area including the drain and source, and enhancing the N- polysilicon of the gate region to N+; depositing cross-over oxide over the field oxide, NMOS transistor being formed, and the PMOS polysilicon active area; removing the cross-over oxide from the PMOS active area; growing oxide over the PMOS active area and depositing nitride thereover; delineating at least a PMOS gate on the polysilicon active area, the removing the oxide and nitride layers except over the PMOS gate; doping the PMOS drain and source P+ while the gate for the PMOS transistor being formed is shielded by the nitride and oxide layer; oxidizing the field oxide, source and drain of the PMOS active area where the crossover oxide was removed; removing the gate nitride and oxide layers to bare polysilicon over the PMOS active area, and growing gate oxide for the PMOS transistor; opening the source, gate, and drain for the NMOS transistor being formed and the source and drain for the PMOS transistor being formed for contacts; and, establishing metal contacts for said source, gate, and drain for the NMOS transistor and said source and drain for the PMOS transistor, and establishing a metal electrode for said PMOS gate.

Claim 2

A method for manufacturing complementary self-aligned NMOS and PMOS stacked transistors using a P doped silicon substrate, comprising the steps of: selectively growing field oxide around an active area on a first surface of the substrate; growing a gate oxide over the active area; depositing a layer of undoped polysilicon over the first surface, followed by recrystallization of the polysilicon; doping the polysilicon N-; delineating an N gate region for the NMOS transistor being formed from the polysilicon layer and an active area from the polysilicon layer on the field oxide for the PMOS transistor being formed; outlining the NMOS active area for the NMOS transistor being formed; ion implanting N+ dopant in the outlined NMOS area including the drain and source, and enhancing the N- polysilicon of the gate region to N+; depositing cross-over oxide over the field oxide, NMOS transistor being formed, and the PMOS polysilicon active area; removing the cross-over oxide from the PMOS active area; growing oxide over the PMOS active area and depositing nitride thereover; delineating at least a PMOS gate on the polysilicon active area, the removing the oxide and nitride layers except over the PMOS gate; doping the PMOS drain and source P+ while the gate for the PMOS transistor being formed is shielded by the nitride and oxide layer; oxidizing the field oxide, source and drain of the PMOS active area where the crossover oxide was removed; removing the gate nitride and oxide layers to bare polysilicon over the PMOS active area, and growing gate oxide for the PMOS transistor; opening the source, gate, and drain for the NMOS transistor being formed and the source and drain for the PMOS transistor being formed for contacts; and, establishing metal contacts for said source, gate, and drain for the NMOS transistor and said source and drain for the PMOS transistor, and establishing a metal electrode for said PMOS gate.

Claim 3

A method for manufacturing complementary self-aligned NMOS and PMOS stacked transistors using a P doped silicon substrate, comprising the steps of: growing an oxide layer on a first surface of said substrate and depositing a nitride layer on the oxide layer; using a first mask to delineate an active area for the NMOS transistor being formed; retaining the oxide layer and nitride layer over the active area while removing the rest of the nitride and oxide layers; growing field oxide around the active area and then removing the nitride and oxide layers from the active area and growing a gate oxide over the active area; depositing a layer of undoped polysilicon over the field oxide and the gate oxide, followed by recrystallization of the polysilicon; doping the polysilicon N-; using a second mask for delineating an N gate region for the NMOS transistor being formed from the polysilicon layer and an active area from the polysilicon layer on the field oxide for the PMOS transistor being formed; using a third mask to outline the NMOS active area for the NMOS transistor being formed; ion implanting N+ dopant in the outlined NMOS area including the drain and source, and enhancing the N- polysilicon of the gate region to N+; depositing cross-over oxide over the field oxide, NMOS transistor being formed, and the PMOS polysilicon active area; removing the cross-over oxide from the PMOS active area under control of a fourth mask; growing oxide over the PMOS active area and depositing nitride thereover; using a fifth mask to define at least a PMOS gate on the polysilicon active areas, and removing the oxide and nitride layers except under this mask; doping the PMOS drain and source P+ while the gate for the PMOS is shielded by the nitride and oxide layer; oxidizing the field oxide, source and drain of the PMOS active area where the crossover oxide was removed; removing the gate nitride and oxide layers to bare polysilicon over the PMOS active area, and growing gate oxide for the PMOS transistor; using a sixth mask to open the source, gate, and drain for the NMOS transistor being formed and the source and drain for the PMOS transistor being formed for contacts; and, establishing metal contacts for said source, gate, and drain for the NMOS transistor and said source and drain for the PMOS transistor, and establishing a metal electrode for said PMOS gate.

Claim 4

A method for manufacturing complementary self-aligned NMOS and PMOS stacked transistors using a P doped silicon substrate, comprising the steps of: growing an oxide layer on a first surface of said substrate and depositing a nitride layer on the oxide layer; using a first mask to delineate an active area for the NMOS transistor being formed; retaining the oxide layer and nitride layer over the active area while removing the rest of the nitride and oxide layers; growing field oxide around the active area and then removing the nitride and oxide layers from the active area and growing a gate oxide over the active area; depositing a layer of undoped polysilicon over the field oxide and the gate oxide, followed by recrystallization of the polysilicon; doping the polysilicon N-; using a second mask for delineating an N gate region for the NMOS transistor being formed from the polysilicon layer and an active area from the polysilicon layer on the field oxide for the PMOS transistor being formed; using a third mask to outline the NMOS active area for the NMOS transistor being formed; ion implanting N+ dopant in the outlined NMOS area including the drain and source, and enhancing the N- polysilicon of the gate region to N+; depositing cross-over oxide over the field oxide, NMOS transistor being formed, and the PMOS polysilicon active area; removing the cross-over oxide from the PMOS active area under control of a fourth mask; growing oxide over the PMOS active area and depositing nitride thereover; using a fifth mask to define at least a PMOS gate on the polysilicon active areas, and removing the oxide and nitride layers except under this mask; doping the PMOS drain and source P+ while the gate for the PMOS is shielded by the nitride and oxide layer; oxidizing the field oxide, source and drain of the PMOS active area where the crossover oxide was removed; removing the gate nitride and oxide layers to bare polysilicon over the PMOS active area, and growing gate oxide for the PMOS transistor; using a sixth mask to open the source, gate, and drain for the NMOS transistor being formed and the source and drain for the PMOS transistor being formed for contacts; and, establishing metal contacts for said source, gate, and drain for the NMOS transistor and said source and drain for the PMOS transistor, and establishing a metal electrode for said PMOS gate.