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US4593393A
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Quasi parallel cyclic redundancy checker
Assignee: General Dynamics Mission Systems Inc
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Filing: 1984-02-06
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Granted: 1986-06-03
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Expires: 2004-02-06
Abstract
Abstract Method and apparatus for operating a CRC in a parallel, quasi parallel or serial fashion. The device allows all the bits in a word to be read and loaded into the cyclic redundancy checker (CRC) register in one clock cycle putting it in sync with the rest of the system. The CRC consists of a set of logic gates for converting a parallel input signal to a converted parallel input signal that is the equivalent of the conversion performed on the serial data input into the prior art cyclic redundancy checkers. The bits of the converted parallel input signal are then combined in another set of logic gates to provide the CRC output.
Inventors
- 👤 Barry B. Mead
- 👤 Gerald V. Piosenka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:05
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/09; H03M13/091
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
254 words
A clocked cyclic redundancy checker (CRC) wherein less than a whole parallel input signal received by said CRC is converted by a single clock pulse, said CRC having a parallel input, a clock input and an output, comprising: multiplexer means for selecting a portion of said parallel input signal received by said CRC to be converted, said multiplexer means having a parallel input coupled to said parallel input of said CRC, a clock input coupled to said clock input of said CRC, and a parallel output; a plurality of first logic gates for converting the selected portion of said parallel input signal to a converted parallel input signal, said plurality of first logic gates having a first parallel input coupled to said parallel output of said multiplexer means, a second parallel input, and a parallel output; register means for storing said converted parallel input signal, said register means having a parallel input, a parallel output and a clock input, said parallel input being coupled to said parallel output of said plurality of first logic gates, said clock input being coupled to said clock input of said CRC and said parallel output being coupled to said second parallel input of said plurality of first logic gates; and combining means for combining said converted parallel input signal to form a CRC signal, said combining means having a parallel input and an output, said parallel input being coupled to said parallel output of said register means and said output being coupled to said output of said CRC.
Claim 2
Dependent Claim
254 words
A clocked cyclic redundancy checker (CRC) wherein less than a whole parallel input signal received by said CRC is converted by a single clock pulse, said CRC having a parallel input, a clock input and an output, comprising: multiplexer means for selecting a portion of said parallel input signal received by said CRC to be converted, said multiplexer means having a parallel input coupled to said parallel input of said CRC, a clock input coupled to said clock input of said CRC, and a parallel output; a plurality of first logic gates for converting the selected portion of said parallel input signal to a converted parallel input signal, said plurality of first logic gates having a first parallel input coupled to said parallel output of said multiplexer means, a second parallel input, and a parallel output; register means for storing said converted parallel input signal, said register means having a parallel input, a parallel output and a clock input, said parallel input being coupled to said parallel output of said plurality of first logic gates, said clock input being coupled to said clock input of said CRC and said parallel output being coupled to said second parallel input of said plurality of first logic gates; and combining means for combining said converted parallel input signal to form a CRC signal, said combining means having a parallel input and an output, said parallel input being coupled to said parallel output of said register means and said output being coupled to said output of said CRC.
Claim 3
Dependent Claim
30 words
The clocked CRC of claim 1 wherein said plurality of first logic gates comprises 3×M logic gates where M is defined as the number of bits read per clock pulse.
Claim 4
Dependent Claim
63 words
The clocked CRC of claim 2 wherein said register means comprises a plurality of flip-flops each having an input, an output and a clock input, said input being coupled to said parallel input of said register means, said output being coupled to said parallel output of said register means and said clock input being coupled to said clock input of said register means.
Claim 5
Dependent Claim
28 words
The clocked CRC of claim 3 wherein said register means comprises 2×N flip-flops, N being defined as the number of bits in said parallel input of said CRC.
Claim 6
Dependent Claim
73 words
The clocked CRC of claim 4 wherein said combining means comprises: a plurality of second logic gates each having an input and an output, said input being coupled to said parallel input of said combining means; and a third logic gate having an input and an output, said input being coupled to said output of said plurality of second logic gates and said output being coupled to said output of said combining means.
Claim 7
Dependent Claim
30 words
The CRC of claim 5 wherein said combining means comprises N÷4 second logic gates, N being defined as the number of said flip-flops in said register means of said CRC.
Claim 8
Dependent Claim
37 words
The clocked CRC of claim 6 wherein said multiplexer means comprises M multiplexers, M being defined as the number of bits in the portion of said parallel input of said CRC read per pulse of said clock.
Claim 9
Dependent Claim
23 words
The CRC of claim 7 wherein said conversion means converts said parallel input of said CRC into an 8 bit converted parallel input.
Claim 10
Dependent Claim
23 words
The CRC of claim 7 wherein said conversion means converts said parallel input of said CRC into a 4 bit converted parallel input.
Claim 11
Dependent Claim
23 words
The CRC of claim 7 wherein said conversion means converts said parallel input of said CRC into a two bit converted parallel signal.
Claim 12
Independent Claim
131 words
A method for transferring a word comprising 8 bits from a parallel data bus to a cyclic redundancy checker (CRC), comprising the steps of: transferring a first set of eight bits of data into a first set of eight registers of said CRC on a first pulse of said clock; moving said first set of eight bits of data into a second set of eight registers of said CRC on a subsequent pulse of said clock; loading a second set of eight bits of data into said first set of eight registers of said CRC on said subsequent pulse of said clock; and repeating the moving and loading of said data each time said clock is triggered until X bits of data have been loaded into the registers of said CRC.
Claim 13
Independent Claim
131 words
A method for transferring a word comprising 8 bits from a parallel data bus to a cyclic redundancy checker (CRC), comprising the steps of: transferring a first set of eight bits of data into a first set of eight registers of said CRC on a first pulse of said clock; moving said first set of eight bits of data into a second set of eight registers of said CRC on a subsequent pulse of said clock; loading a second set of eight bits of data into said first set of eight registers of said CRC on said subsequent pulse of said clock; and repeating the moving and loading of said data each time said clock is triggered until X bits of data have been loaded into the registers of said CRC.
Claim 14
Dependent Claim
357 words
A clocked cyclic redundancy checker (CRC) having a parallel input and an output, comprising: conversion means for converting a parallel input signal of said clocked CRC producing a converted parallel signal, said conversion means having a first parallel input, a second parallel input and a parallel output, said first parallel input being coupled to said parallel input of said clocked CRC; a multi-bit register for receiving and storeing said converted parallel signal from said conversion means, said multi-bit register having a clock input, a parallel input coupled to said parallel output of said conversion means, a parallel output coupled to said second parallel input of said conversion means, a first set and a second set of flip-flops, said first set of flip-flops having a parallel input, a parallel output and a clock input, said parallel input being coupled to said parallel input of said multi-bit register means, said parallel output being coupled to said parallel output of said multi-bit register means, said clock input being coupled to said clock input of said multi-bit register means, said second set of flip-flops having a parallel input, a parallel output and a clock input, said parallel input being coupled to said parallel output of said first set of flip-flops, said parallel output being coupled to said parallel output of said multi-bit register means, and said clock input being coupled to said clock input of said multi-bit register means; a plurality of second logic gates, each having an input and an output, said input being coupled to said parallel output of said multi-bit register means; a third logic gate having an input and an output, said input being coupled to said output of said plurality of second logic gates and said output being coupled to said output of said clocked CRC; and a clock coupled to said clock input of said multi-bit register for controlling the loading of said converted parallel signal from said conversion means into said first set of flip-flops of said multi-bit register and controlling the transfer of said converted parallel signal from said first set of flip-flops to said second set of flip-flops of said multi-bit register.
Claim 15
Dependent Claim
357 words
A clocked cyclic redundancy checker (CRC) having a parallel input and an output, comprising: conversion means for converting a parallel input signal of said clocked CRC producing a converted parallel signal, said conversion means having a first parallel input, a second parallel input and a parallel output, said first parallel input being coupled to said parallel input of said clocked CRC; a multi-bit register for receiving and storeing said converted parallel signal from said conversion means, said multi-bit register having a clock input, a parallel input coupled to said parallel output of said conversion means, a parallel output coupled to said second parallel input of said conversion means, a first set and a second set of flip-flops, said first set of flip-flops having a parallel input, a parallel output and a clock input, said parallel input being coupled to said parallel input of said multi-bit register means, said parallel output being coupled to said parallel output of said multi-bit register means, said clock input being coupled to said clock input of said multi-bit register means, said second set of flip-flops having a parallel input, a parallel output and a clock input, said parallel input being coupled to said parallel output of said first set of flip-flops, said parallel output being coupled to said parallel output of said multi-bit register means, and said clock input being coupled to said clock input of said multi-bit register means; a plurality of second logic gates, each having an input and an output, said input being coupled to said parallel output of said multi-bit register means; a third logic gate having an input and an output, said input being coupled to said output of said plurality of second logic gates and said output being coupled to said output of said clocked CRC; and a clock coupled to said clock input of said multi-bit register for controlling the loading of said converted parallel signal from said conversion means into said first set of flip-flops of said multi-bit register and controlling the transfer of said converted parallel signal from said first set of flip-flops to said second set of flip-flops of said multi-bit register.
Claim 16
Dependent Claim
82 words
The clocked CRC of claim 12 wherein said conversion means comprises a plurality of first logic gates, each having an input and an output, for converting said parallel input of said clocked CRC by combining said parallel input of said clocked CRC with said output from a portion of said plurality of first logic gates and with said second parallel input of said conversion means, said output of said first logic gates being coupled to said parallel output of said conversion means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-02 | 1989-12-02 | 1990-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-02 | 1993-12-02 | 1994-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-02 | 1997-12-02 | 1998-06-03 | $7700.00 | Window Closed / Lapsed |