US4592044A
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US
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Apparatus and method for checking time slot integrity of a switching system
Assignee: Avaya Technology LLC
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Filing: 1984-05-22
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Granted: 1986-05-27
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Expires: 2004-05-22
Abstract
Abstract Apparatus and method are disclosed for checking the time slot data word integrity of data communications in a time multiplexed communication system. A predetermined control bit of each data word of a data frame is alternately switched from its normal control bit function to a bit of a pseudo random sequence (PRS) for time slot data word integrity checking. During alternate data frames a checking circuit compares the predetermined bit of received consecutive data words against consecutive bits of a reference PRS and outputs a time slot cross connect error signal when a difference occurs.
Inventors
- 👤 James J. Ferenc
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:52
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04J; H04J3/00; H04J3/02; H04J3/14; H04L; H04L1/00; H04L1/24; H04L1/241; H04L1/242; H04L1/243; H04M; H04M3/00; H04M3/22; H04M3/24; H04M3/244
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
151 words
A time slot integrity circuit adapted for connection to a time mutiplexed communication system for checking the time slot ordering of data words in a data frame, said integrity circuit comprising means for transmitting over communication apparatus N first type data frames each including multiple data words followed by a second type data frame including multiple data words with each consecutive data word having a predetermined bit which is a consecutive bit of a pseudo random binary sequence, and means for checking said predetermined bit of each consecutive data word of said second type data frame received over said communication apparatus from said transmitting means against an associated consecutive bit of said pseudo random binary sequence and generating an error signal when any said predetermined bit of any of the received data words of said second type data frame differs from the associated consecutive bit of said pseudo random binary sequence.
Claim 2
Dependent Claim
151 words
A time slot integrity circuit adapted for connection to a time mutiplexed communication system for checking the time slot ordering of data words in a data frame, said integrity circuit comprising means for transmitting over communication apparatus N first type data frames each including multiple data words followed by a second type data frame including multiple data words with each consecutive data word having a predetermined bit which is a consecutive bit of a pseudo random binary sequence, and means for checking said predetermined bit of each consecutive data word of said second type data frame received over said communication apparatus from said transmitting means against an associated consecutive bit of said pseudo random binary sequence and generating an error signal when any said predetermined bit of any of the received data words of said second type data frame differs from the associated consecutive bit of said pseudo random binary sequence.
Claim 3
Dependent Claim
32 words
The time slot integrity circuit of claim 1 including memory means for storing data words received from said transmitting means and for outputting said data words for transmission to said checking means.
Claim 4
Dependent Claim
61 words
The time slot integrity circuit of claim 2 wherein said transmitting means and said checking means are colocated, wherein any time delay between data words received from said memory outputting means and data words transmitted from said transmitting means is equal to an integral number of frames, and wherein said pseudo random binary sequence is derived from a common signal source.
Claim 5
Dependent Claim
21 words
The time slot integrity circuit of claim 1 wherein said transmitting means and said checking means are colocated in said circuit.
Claim 6
Dependent Claim
34 words
The time slot integrity circuit of claim 1 including means for selecting said predetermined bits from said data words received from said transmitting means and for transmitting said predetermined bits to said checking means.
Claim 7
Dependent Claim
14 words
The time slot integrity circuit of claim 1 where N is equal to 1.
Claim 8
Dependent Claim
24 words
The time slot integrity circuit of claim 1 wherein said checking means includes means for determining which received data word caused said error signal.
Claim 9
Dependent Claim
27 words
The time slot integrity circuit of claim 1 wherein said predetermined bit is a control bit of each consecutive data word in said first type data frame.
Claim 10
Dependent Claim
54 words
The time slot integrity circuit of claim 8 further including on-line detection means for detecting the contents of said predetermined bit of said first or said second type data frame and for determining a data frame where consecutive predetermined bits are at the same binary state for a fixed number of consecutive data words.
Claim 11
Dependent Claim
129 words
In a time multiplexed communication system, a method for checking the time slot ordering of data words, comprising the steps of: transmitting a first type data frame including multiple data words and transmitting a second type data frame after N of said first type data frames including multiple data words with each consecutive data word having a predetermined bit which is a consecutive bit of a pseudo random binary sequence, and checking said predetermined bits of consecutive data words of a received data frame against consecutive bits of said pseudo random binary sequence and generating an error signal when any of said predetermined bits of any of said received data words of said second type data frame differs from the associated consecutive bit of said pseudo random binary sequence.
Claim 12
Dependent Claim
129 words
In a time multiplexed communication system, a method for checking the time slot ordering of data words, comprising the steps of: transmitting a first type data frame including multiple data words and transmitting a second type data frame after N of said first type data frames including multiple data words with each consecutive data word having a predetermined bit which is a consecutive bit of a pseudo random binary sequence, and checking said predetermined bits of consecutive data words of a received data frame against consecutive bits of said pseudo random binary sequence and generating an error signal when any of said predetermined bits of any of said received data words of said second type data frame differs from the associated consecutive bit of said pseudo random binary sequence.
Claim 13
Dependent Claim
26 words
The method of claim 10 including the step of: storing data words transmitted during said transmitting step and outputting said data words to said checking step.
Claim 14
Dependent Claim
31 words
The method of claim 10 including the step of: selecting said predetermined bits from said data words transmitted during said transmitting step and transmitting said predetermined bits to said checking step.
Claim 15
Dependent Claim
18 words
The method of claim 10 where said transmitting step alternately transmits said first and second type data frames.
Claim 16
Dependent Claim
22 words
The method of claim 10 wherein said checking step includes the step of determining which received data word caused said error signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1989-05-26 | 1989-11-25 | 1990-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-26 | 1993-11-25 | 1994-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-26 | 1997-11-25 | 1998-05-27 | $7700.00 | Window Closed / Lapsed |