Detection of errors in digital signals

Claim 3

A method as set forth in claim 1, in which said comparing step comprises comparing a particular digit with j digits each preceding that digit by a particular spacing (where j is an integer at least equal to two), wherein n equals j + 1 and said omitting step comprises omitting j digits in every n for use as the particular digit.

Claim 4

A method as set forth in claim 2, wherein j is two and said repeating step comprises taking every third digit in the received pattern as the said particular digit.

Claim 5

A method as set forth in claim 1, wherein in said comparing and repeating steps every digit in the received pattern is compared by having at some instant one identity selected from the group consisting of the said "particular digit" and one of the said "at least two digits preceding that digit by the said particular spacing".

Claim 6

A method as set forth in claim 1, wherein said received pattern is a pseudo-random binary sequence of maximal length.

Claim 7

An error detection circuit comprising: input means arranged to receive a serial pattern of digits in which each digit, as transmitted, is a predetermined function of at least two digits each preceding that digit by a particular spacing in the pattern, digit-combining means connected to said input means to combine at least two digits in accordance with said predetermined function, comparison means connected to said input means and said digit-combining means to compare a particular digit in the received pattern with the combination at the output of said digit-combining means of said at least two digits preceding that digit by the said particular spacing, error-indication output means connected to the output of said comparison means arranged to transmit an error indication in the absence of correlation between the inputs of the comparison means, and wherein the improvement comprises the provision of: digit selection means constituting said input means and adapted to select particular digits from the received pattern for comparison and to omit at least one digit in every n (where n is an integer greater than two) for use as the said particular digit.

Claim 8

An error detection circuit comprising: input means arranged to receive a serial pattern of digits in which each digit, as transmitted, is a predetermined function of at least two digits each preceding that digit by a particular spacing in the pattern, digit-combining means connected to said input means to combine at least two digits in accordance with said predetermined function, comparison means connected to said input means and said digit-combining means to compare a particular digit in the received pattern with the combination at the output of said digit-combining means of said at least two digits preceding that digit by the said particular spacing, error-indication output means connected to the output of said comparison means arranged to transmit an error indication in the absence of correlation between the inputs of the comparison means, and wherein the improvement comprises the provision of: digit selection means constituting said input means and adapted to select particular digits from the received pattern for comparison and to omit at least one digit in every n (where n is an integer greater than two) for use as the said particular digit.

Claim 9

A circuit as set forth in claim 6, wherein said digit selection means comprises: digit distributing means arranged to receive said serial pattern, and a plurality of shift registers connected to the output of said digit distributing means, said digit distributing means connected to said shift registers being adapted to divide the digits of the received pattern between the registers.

Claim 10

A circuit as set forth in claim 6, wherein said digit-combining means comprises at least one modulo-2 adder.

Claim 11

A circuit as set forth in claim 6, wherein said digit selection means comprises: digit distributing means arranged to receive said serial pattern, and a plurality of shift registers connected to the output of said digit distributing means, said digit distributing means connected to said shift registers being adapted to divide the digits of the received pattern between the registers, at least one modulo-2 adder constituting said digit-combining means, and connection means connecting said digit selection means to said at least one modulo-2 adder wherein said connecting means connects said at least one modulo-2 adder to any particular shift register of the plurality by a single connection only.