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US4591981A
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Multimicroprocessor system
Assignee: V M E I "Lenin" Quartal Darvenitza
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Filing: 1983-04-26
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Granted: 1986-05-27
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Expires: 2003-04-26
Abstract
Abstract A multimicroprocessor system constructed of multimicroprocessor structures each including N-number of microprocessor units, a shared memory, an input/output unit and a register exchange circuit. The microprocessor units are uniform and include a microprocessor, a data memory, a parallel input-output interface, a sequential input/output circuit, a program memory and a bi-directional buffer. The buffer connects the internal data bus in the microprocessor unit to the shared instruction bus for the multimicroprocessor structure, and the enable inputs of the buffer are connected to the internal busses for circuit selection in the microprocessor unit by the microprocessor address lines. The address lines of the first microprocessor unit in the multimicroprocessor structure are connected also to a shared memory, input/output unit and both to the parallel data exchange register circuit and the "HALT" inputs of the microprocessors in the rest of the units through a logic circuit, which serves to switch off the microprocessor units. The multimicroprocessor structures are connected therebetween by first level data exchange register circuits, whose control inputs are connected to the address lines of the first microprocessor units in the respective first microprocessor structures. These first level register circuits are connected groupwise to a second level data exchange register circuit, whose control input is connected to the address lines of the microprocessor unit whose address lines are connected to the first of the first level data exchange register circuits.
Inventors
- 👤 Nikola K. Kassabov
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17343; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06F9/30003; G06F9/30076; G06F9/30079; G06F9/3887; G06F9/3889
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
340 words
A multimicroprocessor system having a plurality of multimicroprocessor structures, each multimicroprocessor structure including N-number of microprocessor units coupled, collectively, to shared memory units and a shared input/output of the multimicroprocessor structure, said microprocessor units being the same and each microprocessor unit including a microprocessor, a data memory, a parallel input/output interface, a sequential input/output and a program memory; wherein said multimicroprocessor structures further comprise respective parallel data exchange register circuits to which the microprocessor units in each multimicroprocessor structure are respectively connected, said parallel data exchange register circuits having respective additional input/outputs; said multimicroprocessor system further comprising first level data exchange register circuits, to which said additional input/outputs of said parallel data exchange register circuits are connected, each first level data exchange register circuit having a control input, connected to address lines in a first of the microprocessor units in a first of said multimicroprocessor structures, and further additional input/outputs, and said multimicroprocessor system further comprising a second level data exchange register circuit, to which said further additional input/outputs of said first level data exchange register circuits are connected, said second level data exchange register circuit having a control input connected to the address lines in the first of the microprocessor units in the first of said multimicroprocessor structures in a first of said first level data exchange register circuits; and each of said microprocessor units further comprising a bi-directional buffer which serves to connect an internal data bus to a shared instruction bus in said multimicroprocessor structure for all of the microprocessor units, the buffer having enable inputs connected to internal busses for circuit selection in the microprocessor unit by the address lines of the microprocessor unit, the address lines of the first microprocessor unit being connected also to the shared memory units in the multimicroprocessor structure, to the shared input/output as well as both to the respective parallel data exchange register circuits and "HALT" inputs of microprocessors in the other microprocessor units in each multimicroprocessor structure through a logic circuit, which serves to switch off the microprocessor units.
Claim 2
Dependent Claim
340 words
A multimicroprocessor system having a plurality of multimicroprocessor structures, each multimicroprocessor structure including N-number of microprocessor units coupled, collectively, to shared memory units and a shared input/output of the multimicroprocessor structure, said microprocessor units being the same and each microprocessor unit including a microprocessor, a data memory, a parallel input/output interface, a sequential input/output and a program memory; wherein said multimicroprocessor structures further comprise respective parallel data exchange register circuits to which the microprocessor units in each multimicroprocessor structure are respectively connected, said parallel data exchange register circuits having respective additional input/outputs; said multimicroprocessor system further comprising first level data exchange register circuits, to which said additional input/outputs of said parallel data exchange register circuits are connected, each first level data exchange register circuit having a control input, connected to address lines in a first of the microprocessor units in a first of said multimicroprocessor structures, and further additional input/outputs, and said multimicroprocessor system further comprising a second level data exchange register circuit, to which said further additional input/outputs of said first level data exchange register circuits are connected, said second level data exchange register circuit having a control input connected to the address lines in the first of the microprocessor units in the first of said multimicroprocessor structures in a first of said first level data exchange register circuits; and each of said microprocessor units further comprising a bi-directional buffer which serves to connect an internal data bus to a shared instruction bus in said multimicroprocessor structure for all of the microprocessor units, the buffer having enable inputs connected to internal busses for circuit selection in the microprocessor unit by the address lines of the microprocessor unit, the address lines of the first microprocessor unit being connected also to the shared memory units in the multimicroprocessor structure, to the shared input/output as well as both to the respective parallel data exchange register circuits and "HALT" inputs of microprocessors in the other microprocessor units in each multimicroprocessor structure through a logic circuit, which serves to switch off the microprocessor units.
Claim 3
Dependent Claim
258 words
A multimicroprocessor system as claimed in claim 1, wherein the parallel data exchange register circuits each comprise N-number of interconnected registers, a combination circuit and bi-directional busses for input/output of data to the registers, wherein /log 2 (N+1)/ number of control inputs, i.e. the smallest natural number not less than log 2 (N+1), are provided to the combination circuit with the outputs of said combination circuit connected to enable circuits for parallel connection between registers, where a first of said outputs is connected to an enable circuit for connection between an output of a first of said registers and an input of a second of said registers, a second of said outputs is connected to an enable circuit for connection between an output of a third of said registers and an input of the second register, and a (N-3) th of said outputs is connected to an enable circuit for connection between the first register output and an input of the next to the last register, an (N-2) th of said outputs is connected to an enable circuit for connection between an output of a last of said registers and the next to the last register input, a (N-1) th of said outputs is connected to an enable circuit for connection between the first register output and an input of the last register, and an N th of said outputs is connected so as to enable the connection between the second register output and the first register input, where the first register is provided with said additional input/output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-26 | 1989-11-25 | 1990-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-26 | 1993-11-25 | 1994-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-26 | 1997-11-25 | 1998-05-27 | $7700.00 | Window Closed / Lapsed |