Digital to analog converter utilizing pulse width modulation

Claim 2

A digital-to-analog converter comprising: N input terminals for receiving respective bits of an N bit digital word made up of K least significant bits and N-K most significant bits, and representing a sample of an analog signal to be generated; a source of a sample clock signal at frequency f s and having period P; input memory means responsive to the sample clock signal to store the values at the N input terminals as a first digital word; a source of a reload clock signal at frequency f r =(2 K )f s and synchronized with the sample clock signal; a source of a count clock at frequency f c =(2 N )f s and synchronized with the sample clock; a down counter responsive to the reload clock signal to copy the N-K most significant bit values from the input memory as a second digital word and responsive to the count clock signal to decrement the second digital word by ones to zero, and having N-K output terminals at which the second digital word values are output; and means for producing an output signal having a first level while the second digital word is positive and continuing to have the first level during one period of the count clock after the second word is decremented to zero in each of J periods of the reload clock per period of the sample clock, where J is the value of the K least significant bits, and otherwise having a second level.

Claim 3

Apparatus in claim 1 wherein K=2.

Claim 4

Apparatus in claim 1 wherein said means for producing an output signal comprises a ring counter.

Claim 5

Apparatus in claim 3 wherein said means for producing an output signal further comprises a one count delay means.

Claim 6

Apparatus in claim 4 wherein the J times in each period P said output signal has said first value are the first J times said decremented word is zero.

Claim 7

Apparatus in claim 2 wherein said means for producing an output signal comprises a ring counter.

Claim 8

Apparatus in claim 6 wherein said means for producing an output signal further comprises a one count delay means.

Claim 9

Apparatus in claim 7 wherein the J times in each period P said output signal has said first value are the first J times said decremented word is zero.

Claim 10

A digital-to-analog converter comprising: N input terminals for receiving respective bits of an N bit digital word made up of K least significant bits and N-K most significant bits, and representing a sample of an analog signal to be generated; a source of a sample clock signal at frequency f s and having period P; input memory means responsive to the sample clock signal to store the values at the N input terminals as a first digital word; a source of a reload clock signal at frequency f r =(2 K-1 )f s and synchronized with the sample clock signal; a source of a count clock at frequency f c =(2 N-1 )f s and synchronized with the sample clock; a down counter responsive to the reload clock signal to copy the N-K most significant bit values from the input memory as a second digital word and responsive to the count clock signal to decrement the second digital word by ones to zero, and having N-K output terminals at which the second digital word values are output; and means for producing an output signal having a first level while the second digital word is positive and continuing to have the first level during one period of the count clock after the second word is decremented to zero in each of J periods of the reload clock per period of the sample clock, where J is the value of the K-1 most significant bits of the K least significant bits, and, when the LSB=1, continuing to have the first level during one-half period of the count clock in an additional period of the reload clock per period of the sample clock, and otherwise having a second level.

Claim 11

A digital-to-analog converter comprising: N input terminals for receiving respective bits of an N bit digital word made up of K least significant bits and N-K most significant bits, and representing a sample of an analog signal to be generated; a source of a sample clock signal at frequency f s and having period P; input memory means responsive to the sample clock signal to store the values at the N input terminals as a first digital word; a source of a reload clock signal at frequency f r =(2 K-1 )f s and synchronized with the sample clock signal; a source of a count clock at frequency f c =(2 N-1 )f s and synchronized with the sample clock; a down counter responsive to the reload clock signal to copy the N-K most significant bit values from the input memory as a second digital word and responsive to the count clock signal to decrement the second digital word by ones to zero, and having N-K output terminals at which the second digital word values are output; and means for producing an output signal having a first level while the second digital word is positive and continuing to have the first level during one period of the count clock after the second word is decremented to zero in each of J periods of the reload clock per period of the sample clock, where J is the value of the K-1 most significant bits of the K least significant bits, and, when the LSB=1, continuing to have the first level during one-half period of the count clock in an additional period of the reload clock per period of the sample clock, and otherwise having a second level.

Claim 12

Apparatus in claim 9 wherein K=3.

Claim 13

Apparatus in claim 9 wherein said means for producing an output signal comprises a ring counter; a one count delay means; and a one-half count delay means.

Claim 14

Apparatus in claim 11 wherein signals from said ring counter, said one count delay means, and said one-half count delay means cause said output signal to have said first value for one clock period after said decremented word is zero exactly J times in each period P and, when the least significant bit equals one, for one-half clock period exactly one additional time.

Claim 15

Apparatus in claim 12 wherein the J times in each period said output signal remains at said first value for one clock period after said decremented word is zero are the first J times said decremented word is zero and the one time said output signal has said first value for one-half clock period is the (J+1)st time said decremented word is zero.

Claim 16

Apparatus in claim 10 wherein said means for producing an output signal comprises a ring counter; a one count delay means; and a one-half count delay means.

Claim 17

Apparatus in claim 14 wherein signals from said ring counter said one count delay means and said one-half count delay means cause said output signal to have said first value for one clock period after said decremented word is zero exactly J times in each period P and for one-half clock period exactly one time.

Claim 18

Apparatus in claim 15 wherein the J times in each period said output signal remains at said first value for one clock period after said decremented word is zero are the first J times said decremented word is zero and the one time said output signal has said first value for one-half clock period is the (J+1)st time said decremented word is zero.

Claim 19

A digital-to-analog converter comprising: N input terminals for receiving respective bits of an N bit digital word representing a sample of an analog signal to be generated; a source of a sample clock signal at frequency f s and having period P; input memory means responsive to the sample clock signal to store the values at the N input terminals as a first digital word; a source of a reload clock signal at frequency f r =(M)f s and synchronized with the sample clock signal, where M is a positive integer equal to at least 2; a source of a count clock at frequency f c =(2 N )(M)f s and synchronized with the sample clock; a down counter responsive to the reload clock signal to copy the first digital word as a second digital word and responsive to the count clock signal to decrement the second digital word by ones to zero, and having N output terminals at which the second digital word values are output; and means for producing an output signal having a first level while the second digital word is positive, and otherwise having a second level.

Claim 20

A digital-to-analog converter comprising: N input terminals for receiving respective bits of an N bit digital word representing a sample of an analog signal to be generated; a source of a sample clock signal at frequency f s and having period P; input memory means responsive to the sample clock signal to store the values at the N input terminals as a first digital word; a source of a reload clock signal at frequency f r =(M)f s and synchronized with the sample clock signal, where M is a positive integer equal to at least 2; a source of a count clock at frequency f c =(2 N )(M)f s and synchronized with the sample clock; a down counter responsive to the reload clock signal to copy the first digital word as a second digital word and responsive to the count clock signal to decrement the second digital word by ones to zero, and having N output terminals at which the second digital word values are output; and means for producing an output signal having a first level while the second digital word is positive, and otherwise having a second level.

Claim 21

A digital-to-analog converter of the type which, once per sample period at frequency f s , accepts an N-bit digital sample of an analog signal to be generated, divides the N bits into a most significant (N-K) bit portion and a least significant (K) bit remainder portion; allocates each unit of the remainder value to a respective one of 2 K subperiods T of the sample period, and during each of subperiods T, counts at count clock frequency f c =2 N f S , to the (N-K) bit portion value while producing a first level output signal, plus one count if a remainder unit is allocated to that subperiod, and produces a second level output signal for the balance of that subperiod, characterized in that: the circuit produces at most one first level output signal during each subperiod T.

Claim 22

A digital-to-analog converter of the type which, once per sample period at frequency f s , accepts an N-bit digital sample of an analog signal to be generated, divides the N bits into a most significant (N-K) bit portion and a least significant (K) bit remainder portion; allocates each unit of the remainder value to a respective one of 2 K subperiods T of the sample period, and during each of subperiods T, counts at count clock frequency f c =2 N f S , to the (N-K) bit portion value while producing a first level output signal, plus one count if a remainder unit is allocated to that subperiod, and produces a second level output signal for the balance of that subperiod, characterized in that: the circuit produces at most one first level output signal during each subperiod T.