N-ary input to n-1 binary outputs level shift circuit for I2 L

Claim 1

A circuit for level adaptation between an I 2 L circuit and a preceding combinatory logic circuit, comprising a direct current source (11) which is connected to the input of a switch which is controlled in dependence on the level of the output (8) of the combinatory logic circuit (6), characterized in that the circuit is designed for the conversion of n different logic levels on the output of the preceding circuit where n is greater than or equal to 3, the switch comprising n-1 emitter-coupled transistor pairs (91, 101; 92, 102; 93, 103), the base of one transistor (91, 92, 93) of each pair being coupled to the output (8) of the preceding circuit, the collector-emitter current path of each of said one transistor of each pair being respectively connected in series, with the emitter of the first transistor (91) of said transistors connected in series being connected to said current source (11), the collector of the other transistor (101, 102, 103) of each pair being connected to a current mirror (141, 142, 143), the base of each of said other transistor of each pair being respectively connected to a different reference voltage (U 1 ', U 2 ', U 3 '), wherein the reference voltages supplied to said bases of said other transistors of each pair are ordered such that the other transistor (101) of said pair having said one transistor (91) connected to the current source (11), receives the highest reference voltage (U 1 ').