Semiconductor integrated circuit having stacked integrated injection logic circuits

Claim 2

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a direction opposite to said one direction, said second means having a first transistor of pnp type whose base is connected to an output terminal of said given layer and whose emitter is connected to an injector terminal of said given layer, and a second transistor of npn type whose base is connected to a collector of said first transistor for receiving a signal from said first transistor, said second transistor being connected at its collector to an input terminal of said another layer and at its emitter to a reference terminal of said another layer, and a charging circuit having a resistor coupled between said injector terminal of said given layer and the base of said first transistor; and (d) a discharging circuit connected to said base of said second transistor.

Claim 3

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a direction opposite to said one direction, said second means having a first transistor whose base is connected to an output terminal of said given layer and whose emitter is connected to an injector terminal of said given layer, and a second transistor whose base is connected to a collector of said first transistor for receiving a signal from said first transistor, said second transistor being connected at its collector to an input terminal of said another layer and at its emitter to a reference terminal of said another layer, and a charging circuit having a resistor coupled between said injector terminal of said given layer and the base of said first transistor; and (d) a discharging circuit connected to said base of said second transistor.

Claim 4

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a direction opposite to said one direction, said second means having a first transistor whose base is connected to an output terminal of said given layer and whose emitter is connected to an injector terminal of said given layer, and a second transistor whose base is connected to a collector of said first transistor for receiving a signal from said first transistor, said second transistor being connected at its collector to an input terminal of said another layer and at its emitter to a reference terminal of said another layer, and a charging circuit having a resistor coupled between said injector terminal of said given layer and the base of said first transistor; and (d) a discharging circuit connected to said base of said second transistor.

Claim 5

A seminconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL cicuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a one direction opposite to said direction, said second means having a first transistor of npn type whose base is connected to an output terminal of said given layer and whose emitter is connected to a reference terminal of said given layer, a second transistor having a base connected to the collector of said first transistor, an emitter connected to the emitter of said first transistor, and a collector from which said signal from said given layer is derived, and a third transistor of npn type whose base is connected to the collector of said second transistor for receiving a signal from said first transistor, said third transistor being connected at its first collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer; (d) a discharging circuit connected to said base of said third transistor; and (e) a charging circuit comprising an IIL injector transistor coupled between said injector terminal of said given layer and the base of said first transistor.

Claim 6

A seminconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL cicuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a one direction opposite to said direction, said second means having a first transistor of npn type whose base is connected to an output terminal of said given layer and whose emitter is connected to a reference terminal of said given layer, a second transistor having a base connected to the collector of said first transistor, an emitter connected to the emitter of said first transistor, and a collector from which said signal from said given layer is derived, and a third transistor of npn type whose base is connected to the collector of said second transistor for receiving a signal from said first transistor, said third transistor being connected at its first collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer; (d) a discharging circuit connected to said base of said third transistor; and (e) a charging circuit comprising an IIL injector transistor coupled between said injector terminal of said given layer and the base of said first transistor.

Claim 7

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner than an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a one direction opposite to said direction, said second means having a first transistor whose base is connected to an output terminal of said given layer and whose emitter is connected to a reference terminal of said given layer, a second transistor having a base connected to the collector of said first transistor, an emitter connected to the emitter of said first transistor, and a collector from which said signal from said given layer is derived, and a third transistor whose base is connected to the collector of said second transistor for receiving a signal from said first transistor, said third transistor being connected at its collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer; (d) a discharging circuit connected to said base of said third transistor; and (e) a charging circuit comprising an IIL injector transistor coupled between said injector terminal of said given layer and the base of said first transistor.

Claim 8

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner than an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a one direction opposite to said direction, said second means having a first transistor whose base is connected to an output terminal of said given layer and whose emitter is connected to a reference terminal of said given layer, a second transistor having a base connected to the collector of said first transistor, an emitter connected to the emitter of said first transistor, and a collector from which said signal from said given layer is derived, and a third transistor whose base is connected to the collector of said second transistor for receiving a signal from said first transistor, said third transistor being connected at its collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer; (d) a discharging circuit connected to said base of said third transistor; and (e) a charging circuit comprising an IIL injector transistor coupled between said injector terminal of said given layer and the base of said first transistor.

Claim 9

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a direction opposite to said one direction, said second means having a first transistor of npn type whose base is connected to an output terminal of said given layer and whose collector is connected to an injector terminal of said given layer whereby said first transistor is prevented from being saturated, and a second transistor whose base is responsive to a signal from an emitter of said first transistor, said second transistor being connected at its collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer.

Claim 10

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a direction opposite to said one direction, said second means having a first transistor of npn type whose base is connected to an output terminal of said given layer and whose collector is connected to an injector terminal of said given layer whereby said first transistor is prevented from being saturated, and a second transistor whose base is responsive to a signal from an emitter of said first transistor, said second transistor being connected at its collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer.

Claim 11

A semiconductor integrated circuit as claimed in any one of claims 1, 2, 3, 4 or 5 wherein said first means comprises a diode coupled between a collector of an output transistor of one of said layers and a base of an input of another one of said layers.

Claim 12

A semiconductor integrated circuit as claimed in any one of claims 1 or 2, wherein said discharging circuit comprises a constant-current circuit.

Claim 13

A semiconductor integrated circuit as claimed in any one of claims 3 or 4, wherein said discharging circuit comprises a constant-current circuit.

Claim 14

A semiconductor integrated circuit as claimed in claim 8, wherein said constant-current circuit comprises a current-mirror circuit having a IIL structure.

Claim 15

A semiconductor integrated circuit as claimed in claim 9, wherein said current-mirror circuit comprises a pair of transistors each having a base connected to each other, a collector of one of said pair being connected to said bases of said pair, a collector of the other of said pair being connected to said base of said third transistor.

Claim 16

A circuit as recited in claim 5 wherein said first transistor is connected in an emitter follower configuration.

Claim 17

A circuit as recited in claim 4 wherein said discharging circuit comprises a resistor.

Claim 18

A circuit as recited in claim 4 further comprising a diode coupled between said first and second transistors.

Claim 19

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a direction opposite to said one direction, said second means having a first transistor whose base is connected to an output terminal of said given layer and whose emitter is connected to a reference terminal of said given layer, and a second transistor whose base is connected to the collector of said first transistor for receiving a signal from said first transistor, said second transistor being connected its collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer; (d) a discharging circuit connected to said base of said second transistor; and (e) a charging circuit comprising an IIL injector transistor coupled between said injector terminal of said given layer and the base of said first transistor.

Claim 20

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a direction opposite to said one direction, said second means having a first transistor whose base is connected to an output terminal of said given layer and whose emitter is connected to a reference terminal of said given layer, and a second transistor whose base is connected to the collector of said first transistor for receiving a signal from said first transistor, said second transistor being connected its collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer; (d) a discharging circuit connected to said base of said second transistor; and (e) a charging circuit comprising an IIL injector transistor coupled between said injector terminal of said given layer and the base of said first transistor.

Claim 21

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a direction opposite to said one direction, said second means having a first transistor whose base is connected to an output terminal of said given layer and whose emitter is conected to an injector terminal of said given layer, and a second transistor whose base is connected to the collector of said first transistor for receiving a signal from said first transistor, said second transistor being connected at its collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer; (d) a discharging circuit connected to said base of said second transistor; and (e) a charging circuit comprising an IIL injector transistor coupled between said injector terminal of said given layer and the base of said first transistor.

Claim 22

A semiconductor integrated circuit comprising: (a) a plurality of IIL circuits each having a plurality of IIL gates constructed of a plurality of transistors, said IIL circuits being stacked in the form of a multi-layer in such a manner that an injector terminal of an n th layer in the stacked arrangement is connected to a reference terminal of an (n+1) th layer, wherein "n" is an integer; (b) first means for transmitting a signal from each of said layers to another one of said layers in one direction; (c) second means for shifting the level of a signal from a given layer when transmitting said signal to another layer in a direction opposite to said one direction, said second means having a first transistor whose base is connected to an output terminal of said given layer and whose emitter is conected to an injector terminal of said given layer, and a second transistor whose base is connected to the collector of said first transistor for receiving a signal from said first transistor, said second transistor being connected at its collector to an input terminal of said another layer, and at its emitter to a reference terminal of said another layer; (d) a discharging circuit connected to said base of said second transistor; and (e) a charging circuit comprising an IIL injector transistor coupled between said injector terminal of said given layer and the base of said first transistor.

Claim 23

A semiconductor integrated circuit as claimed in claim 14 or 15 wherein said discharging circuit comprises a constant-current circuit.

Claim 24

A semiconductor integrated circuit as claimed in claim 16 wherein said constant-current circuit comprises a current-mirror circuit having a IIL structure.

Claim 25

A semiconductor integrated circuit as claimed in claim 17 wherein said current-mirror circuit comprises a pair of transistors each having a base connected to each other, a collector of one of said pair being connected to said bases of said pair, a collector of the other of said pair being connected to said base of said second transistor.

Claim 26

A semiconductor integrated circuit as claimed in claim any one of claims 3, 4, 14 or 15, wherein said charging circuit comprises a constant-current circuit.

Claim 27

A semiconductor integrated circuit as claimed in claim 19, wherein said constant-current circuit comprises an injector transistor of an IIL circuit.

Claim 28

A semiconductor integrated circuit as claimed in any one of claims 5, 14 or 15, further comprising a diode coupled between said first and second transistors.

Claim 29

A semiconductor integrated circuit as claimed in claim 2, further comprising a power source terminal to which said injector input terminal of said given layer is connected, said given layer being located at the top of the stacked arrangement.