Multilayer interconnection structure for semiconductor device

Claim 1

A multilayer interconnection structure for a semiconductor device comprising: a semiconductor substrate; at least three interconnecting layers and at least two insulating layers deposited on the surface of said substrate with each one of said insulating layers being interposed between adjacent ones of said interconnecting layers; connection means including a plurality of contact holes formed in at least a first one of said at least two insulating layers in order to insure a desired connection between a first and a second of said at least three interconnecting layers wherein said first and second layers are separated by said first insulating layer; and wherein said second interconnecting layer and a third one of said at least three interconnecting layers are spaced from each other by a second one of said at least two insulating layers such that the projection of said third interconnecting layer onto said second interconnecting layer defines an intersecting area above at least one of said plurality of contact holes with the cross-sectional area of said at least one of said contact holes being less than said intersecting area and wherein at least another one of said plurality of contact holes does not have said intersecting area located above it.