Process of manufacturing a high-frequency vertical junction field-effect transistor

Claim 1

A process for manufacturing a high-frequency vertical junction field effect transistor, the structure of which includes an embedded grid constituted by parallel bars, comprising the following steps: successively depositing, on a silicon substrate, layers of first conductivity type silicon oxide of a first thickness, silicon nitride and resin and successively etching these layers so as to form an arrangement of parallel bars of silicon of the first conductivity type protected by nitride and resin; implanting an impurity of a second type of conductivity type, different from the first conductivity type, masked by the three above-described layers, with an energy such that this impurity is implanted at a certain depth within the substrate and forms parallel implanted bars having said second type of conductivity; removing the resin; growing a silicon oxide layer at low temperature between the bars of silicon of the first conductivity type of protected by silicon nitride, this second oxide layer being thicker than the first and contacting the implanted bars of the second type of conductivity; exposing the ends of the bars of the second type of conductivity, removing the silicon nitride and etching the silicon oxide to a thickness corresponding to the first thickness; depositing a polycrystalline silicon layer; separating the polycrystalline silicon layer into first and second zones said first zone being partly in contact with said first conductivity type silicon substrate but not in contact with the ends of said second conductivity type bars, said second zone being doped according to said first conductivity type, said second zone being partly in contact with the ends of the bars of the second type of conductivity but not in contact with the first conductivity type silicon substrate, said second zone being doped with the second type of conductivity.