Semiconductor memory device with improved memory arrangement

Claim 2

A semiconductor memory device, comprising: a plurality of first word lines; a plurality of second word line, said first word lines and said second word lines being interleaved in parallel; a plurality of bit lines intersecting with said word lines; a plurality of memory cells coupled between said word lines and said bit lines; a first decoding circuit; a second decoding circuit; a plurality of control signal terminals; means for operatively supplying one of said control signal terminals with a selection signal; a plurality of first driving transistors each coupled between one of said control signal terminals and one of said first word lines; first means for controlling said first driving transistors in response to an output of said first decoding circuit; a plurality of second driving transistors each coupled between one of said control signal terminals and one of said second word lines; and second means for controlling said second driving transistors in response to an output of said second decoding circuit; wherein every two adjacent word lines are assigned to different decoding circuits.

Claim 3

The memory device according to claim 1, in which said first means includes a plurality of first transfer gate transistors each coupled between the output of said first decoding circuit and a gate of associated one of said first driving transistors, and said second means includes a plurality of second transfer transistors each coupled between the output of said second decoding circuit and a gate of associated one of said second driving transistors.

Claim 4

The memory device according to claim 1, in which one of said first driving transistors and one of said second transistors both connected to the adjacent first and second word lines are commonly connected to the same control signal terminal.

Claim 5

The memory device according to claim 1, in which each of said first and second decoding circuits includes a NOR circuit receiving address signals.

Claim 6

A semiconductor memory device, comprising a first number M (M being an integer of two or more) of decoding circuit; a second number N (N being an integer of two or more) of selection lines, a third number MxN of word lines arranged in parallel; wherein said word lines are classified into N word line groups each including N word lines, a third number MxN of driving transistors, said driving transistors are classified into M transistors groups each including N of driving transistors, one of the driving transistors in each transistor group is electrically coupled between one of the word lines of one of said word line group and one of said selection lines, all the driving transistors in one of said driving transistor group are controlled by one of said decoding circuits, the word lines of one word line group are assigned to one of said decoding circuits and the word lines of at least one other word line group are assigned to at least one other decoding circuit topographically adjacent to said one decoding circuit being interleaved one after the other while the word lines of the same word line group are never adjacent to each other in the topographical relation, said device further comprising a plurality of bit lines, a plurality of memory cells coupled between said word lines and said bit lines, and means for selectively energizing one of said selection lines.

Claim 7

A semiconductor memory device, comprising a first number M (M being an integer of two or more) of decoding circuit; a second number N (N being an integer of two or more) of selection lines, a third number MxN of word lines arranged in parallel; wherein said word lines are classified into N word line groups each including N word lines, a third number MxN of driving transistors, said driving transistors are classified into M transistors groups each including N of driving transistors, one of the driving transistors in each transistor group is electrically coupled between one of the word lines of one of said word line group and one of said selection lines, all the driving transistors in one of said driving transistor group are controlled by one of said decoding circuits, the word lines of one word line group are assigned to one of said decoding circuits and the word lines of at least one other word line group are assigned to at least one other decoding circuit topographically adjacent to said one decoding circuit being interleaved one after the other while the word lines of the same word line group are never adjacent to each other in the topographical relation, said device further comprising a plurality of bit lines, a plurality of memory cells coupled between said word lines and said bit lines, and means for selectively energizing one of said selection lines.

Claim 8

The memory device according to claim 5, in which said selection lines are coupled to drains of said driving transistors.

Claim 9

The memory device according to claim 5, in which the gate of each of said driving transistors is connected to one of said decoding circuits via a drain-source path of a transfer gate transistor.

Claim 10

A semiconductor memory device, comprising a plurality of memory arrays, each of said memory arrays including: a plurality of word lines arranged in parallel, said word lines being classified into a plurality of word line groups; a plurality of bit lines; a plurality of memory cells; a plurality of decoder circuits each provided for each one of said word line groups; a plurality of driving transistor groups each provided for each one of said word line groups, each of said driving transistor groups including the same number of driving transistors as the number of the word lines in each word line group, the driving transistors of each driving transistor group being coupled between said selection lines and the word lines of the associated word line group; means for operatively supplying one of said selection lines with a selection signal; and a plurality of control means each provided for each one of said decoder circuits and one of said driving transistor groups, each of said driving transistors driving the word line coupled thereto when the associated decoder circuit is selected and the associated selection line is supplied with the selection signal therefrom, the word lines of one word line group assigned to one decoder circuit and the word lines of another word line group assigned to another decoder adjacent to said one decoder circuit are interleaved one with the other in topographical relation, the selection lines are electrically common through said plurality of memory arrays, and every two or more consecutively arranged word lines are assigned to different decoder circuits.

Claim 11

A semiconductor memory device, comprising a plurality of memory arrays, each of said memory arrays including: a plurality of word lines arranged in parallel, said word lines being classified into a plurality of word line groups; a plurality of bit lines; a plurality of memory cells; a plurality of decoder circuits each provided for each one of said word line groups; a plurality of driving transistor groups each provided for each one of said word line groups, each of said driving transistor groups including the same number of driving transistors as the number of the word lines in each word line group, the driving transistors of each driving transistor group being coupled between said selection lines and the word lines of the associated word line group; means for operatively supplying one of said selection lines with a selection signal; and a plurality of control means each provided for each one of said decoder circuits and one of said driving transistor groups, each of said driving transistors driving the word line coupled thereto when the associated decoder circuit is selected and the associated selection line is supplied with the selection signal therefrom, the word lines of one word line group assigned to one decoder circuit and the word lines of another word line group assigned to another decoder adjacent to said one decoder circuit are interleaved one with the other in topographical relation, the selection lines are electrically common through said plurality of memory arrays, and every two or more consecutively arranged word lines are assigned to different decoder circuits.

Claim 12

The memory device according to claim 8, in which each of said control means includes a plurality of transfer gate transistors coupled between the output of the associated decoding circuit and the associated set of driving transistors.

Claim 13

The memory device according to claim 8, in which said plurality of memory arrays operate in parallel.

Claim 14

A semiconductor device, comprising: a plurality of drive lines, said drive line being classified into a plurality of drive line groups each including a plurality of drive lines; a plurality of decoding circuits each provided for each of said drive line groups; a plurality of selection terminals; a plurality of driving transistors, said driving transistors being classified into a plurality of transistor groups each provided for each of said drive line groups, each one of the driving transistors in each transistor group being electrically coupled between one of the drive line in each drive line group and one of said selection terminals, all the driving transistors in one of said transistor group being controlled by one of said decoder circuits, each one of the drive lines of one drive line group assigned to one of said decoding circuits being located, in topographical relation, adjacent to each one of the drive lines of at least one other drive line group assigned to at least one other decoding circuit adjacent to said decoding circuit; and means for selectively energizing said selection terminal; wherein at least every two or more adjacent drive lines in the topography are assigned to different decoder circuits.

Claim 15

A semiconductor device, comprising: a plurality of drive lines, said drive line being classified into a plurality of drive line groups each including a plurality of drive lines; a plurality of decoding circuits each provided for each of said drive line groups; a plurality of selection terminals; a plurality of driving transistors, said driving transistors being classified into a plurality of transistor groups each provided for each of said drive line groups, each one of the driving transistors in each transistor group being electrically coupled between one of the drive line in each drive line group and one of said selection terminals, all the driving transistors in one of said transistor group being controlled by one of said decoder circuits, each one of the drive lines of one drive line group assigned to one of said decoding circuits being located, in topographical relation, adjacent to each one of the drive lines of at least one other drive line group assigned to at least one other decoding circuit adjacent to said decoding circuit; and means for selectively energizing said selection terminal; wherein at least every two or more adjacent drive lines in the topography are assigned to different decoder circuits.

Claim 16

The device according to claim 11, wherein each of said driving transistors has a drain-source path coupled between one of said selection lines and one of said drive lines.

Claim 17

The device according to claim 11, wherein a gate of each of said driving transistor is connected to an output of the associated decoder circuit via a transfer gate.