Patent US4584492A successfully refreshed from Google Patents.
US4584492A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Temperature and process stable MOS input buffer
Assignee: Intel Corp
•
Filing: 1984-08-06
•
Granted: 1986-04-22
•
Expires: 2004-08-06
Abstract
Abstract A MOS integrated circuit buffer which operates over a wide temperature range particularly suited for receiving a TTL signal over the range of -55 degrees C. to 155 degrees C. even with expected process variations. A compensated reference potential is developed in a feedback circuit. This reference potential is used to provide compensation to a buffer section which has substantially identical characteristics to the feedback circuit. The trigger point of the buffer section is thus maintained at the reference potential.
Inventors
- 👤 Patrick O. Sharp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
172 words
In an MOS integrated circuit, a buffer for sensing an input signal which varies above and below a reference potential comprising: a first circuit coupled to receive said reference potential, said first circuit providing a buffered reference potential; a first amplifier means for receiving said buffered reference potential at its input; a feedback path coupling the output of said first amplifier means to said first circuit so as to cause said buffered reference potential to maintain said first amplifier means in a predetermined operating range, said first amplifier means thereby providing a compensated reference potential; a second circuit, substantially identical to first circuit, coupled to receive said input signal, said second circuit providing a buffered input signal; a second amplifier means for receiving said buffered input signal at its input and for providing an output signal for said buffer; an electrical path coupling said compensated reference potential to said second circuit thereby providing a compensated input signal; whereby a buffer is realized which operates over a wide temperature and process variation range.
Claim 2
Dependent Claim
172 words
In an MOS integrated circuit, a buffer for sensing an input signal which varies above and below a reference potential comprising: a first circuit coupled to receive said reference potential, said first circuit providing a buffered reference potential; a first amplifier means for receiving said buffered reference potential at its input; a feedback path coupling the output of said first amplifier means to said first circuit so as to cause said buffered reference potential to maintain said first amplifier means in a predetermined operating range, said first amplifier means thereby providing a compensated reference potential; a second circuit, substantially identical to first circuit, coupled to receive said input signal, said second circuit providing a buffered input signal; a second amplifier means for receiving said buffered input signal at its input and for providing an output signal for said buffer; an electrical path coupling said compensated reference potential to said second circuit thereby providing a compensated input signal; whereby a buffer is realized which operates over a wide temperature and process variation range.
Claim 3
Dependent Claim
14 words
The buffer defined by claim 1 wherein said buffer is realized with n-channel transistors.
Claim 4
Dependent Claim
14 words
The buffer defined by claim 1 wherein said first and second circuits are inverters.
Claim 5
Dependent Claim
27 words
The buffer defined by claim 3 wherein said feedback path includes a first field-effect transistor with its gate coupled to said output of said first amplifier means.
Claim 6
Dependent Claim
18 words
The buffer defined by claim 1 or claim 3 wherein said first and second amplifier means are inverters.
Claim 7
Dependent Claim
24 words
The buffer defined by claim 1 or claim 4 wherein said first and second amplifier means are operating in a region of maximum gain.
Claim 8
Dependent Claim
22 words
The buffer defined by claim 1 or claim 4 wherein said first and second amplifier means are operating in a linear region.
Claim 9
Dependent Claim
27 words
The buffer defined by claim 4 wherein said reference potential is derived from a voltage divider which is coupled to the power supply potential for said buffer.
Claim 10
Dependent Claim
182 words
In an MOS integrated circuit, a buffer for sensing an input signal which varies above and below a reference potential comprising: a first inverter coupled to receive said reference potential for providing a buffered reference potential; a second inverter coupled to receive the output of said first inverter; a first field-effect transistor having its gate coupled to the output of said second inverter and one of its other terminals coupled to the input of said second inverter and to said first inverter, for providing feedback between said input and output of said second inverter; a third inverter coupled to receive said input signal for providing a buffered input signal; a fourth inverter coupled to receive the output of said third inverter, the output of said fourth inverter providing the output for said buffer; a second field-effect transistor having its gate coupled to said output of said second inverter and one of its other terminals coupled to said third inverter and to said input of said fourth inverter, whereby a buffer is realized which operates over a wide temperature and process variation range.
Claim 11
Dependent Claim
182 words
In an MOS integrated circuit, a buffer for sensing an input signal which varies above and below a reference potential comprising: a first inverter coupled to receive said reference potential for providing a buffered reference potential; a second inverter coupled to receive the output of said first inverter; a first field-effect transistor having its gate coupled to the output of said second inverter and one of its other terminals coupled to the input of said second inverter and to said first inverter, for providing feedback between said input and output of said second inverter; a third inverter coupled to receive said input signal for providing a buffered input signal; a fourth inverter coupled to receive the output of said third inverter, the output of said fourth inverter providing the output for said buffer; a second field-effect transistor having its gate coupled to said output of said second inverter and one of its other terminals coupled to said third inverter and to said input of said fourth inverter, whereby a buffer is realized which operates over a wide temperature and process variation range.
Claim 12
Dependent Claim
28 words
The buffer defined by claim 9 wherein the sizes of the transistors of said first inverter are identical to the sizes of the transistors of said third inverter.
Claim 13
Dependent Claim
22 words
The buffer defined by claim 10 wherein the size of said first transistors is identical to the size of said second transistor.
Claim 14
Dependent Claim
14 words
The buffer defined by claim 11 wherein said buffer is fabricated from n-channel transistors.
Claim 15
Dependent Claim
51 words
The buffer defined by claim 12 including p-channel transistors coupled to said first and third inverters and said first and second transistors, said p-channel transistors coupled to said third inverter and said second transistor being coupled to a select line to permit selective conduction through said third inverter and second transistor.
Claim 16
Dependent Claim
26 words
The buffer defined by claim 13 wherein said p-channel transistors coupled to said first inverter and said first transistor have their gates permanently coupled to ground.
Claim 17
Dependent Claim
45 words
The buffer defined by claim 14 including a first n-channel transistor coupled to said input of said second inverter and a second n-channel transistor coupled to said input of said fourth inverter, and second n-channel transistor for selectively grounding said input of said fourth inverter.
References Cited (Backward Citations)
DE2549308A1
Cited
US4110641A
Cited
US4199693A
Cited
US4258272A
Cited
US4410813A
Cited
US4437024A
Cited
US4430582A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |