Expansion circuit for digital signals

Claim 1

An expansion circuit for digital signals, said expansion circuit being applied with a digital signal whose data has been compressed in such a manner that a predetermined number of bits are cut off from a plurality of bits forming said digital signal, to expand said compressed data, said expansion circuit comprising: a shift register applied with said compressed digital signal for shifting a plurality of bits forming said compressed digital signal to add one or more bits to said shifted bits at the position following the least significant bit of said shifted bits; judging means applied with said compressed digital signal for judging the number of bits having been cut off in compressing said data, to supply said shift register with information with respect to the number of bits, by which said compressed digital signal is shifted in said shift register, including counter means for changing its count content in response to clock pulses, to generate an output signal when its count content has changed by a predetermined number corresponding to the number of bits to be added; and adding means applied with said information from said judging means, for giving correction data to said one or more added bits, said correction data being a numerical value which is about one half the largest one of numerical values expressed by one or more bits, by which said compressed digital signal is shifted in said shift register.