US3755808A
Expired / Lapsed
US
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Binary-code expander
Assignee: Italtel SpA
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Filing: 1971-09-02
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Granted: 1973-08-28
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Expires: 1991-09-02
Abstract
Abstract A compressed eight-bit word, including a polarity or sign bit Qs, three range-indicating bits a, b, c and a group of four significant bits X, Y, Z, W, is reconverted into an original 12bit word by introducing (7 - n) zeroes between the sign bit Qs and the significant group, with n representing the numerical value of the three-bit combination a, b, c, inserting a 1 just ahead of bit X unless a b c 0, and adding a 1 (followed only by ''''0''s'''') immediately behind bit W if this bit is in other than the No. 12 position. A logic matrix, forming part of a range decoder, receives the bits a, b, c from an eight-stage input register to control the transfer of significant bits X, U, Z, W to consecutive stages of a 12-bit expansion register, along with an immediately preceding 1 if any of the controlling bits has a finite value. This group of bits is followed in the expansion register by at least one 1 whose position determines the extent to which the significant group with its leading 1 must be shifted away from the sign bit Qs invariably tranferred to the first stage of that register.
Inventors
- 👤 G Candiani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:25
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/50
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
163 words
A method of re-expanding a compressed code word, derived from an original code word with a predetermined larger number of bits, into a substantial duplicate of said original code word, said compressed word including a group of significant bits preceded by an m-bit combination identfying one of several amplitude ranges of an analog signal represented by said original code word, comprising the steps of: a. separating said m-bit combination from said group of significant bits; b. prefacing said significant group with up to (2m-1) zeroes, the number n of such zeroes depending upon the numerical value of said m-bit combination; c. inserting a 1 just ahead of said group of significant bits upon said numerical value identifying any but the lowest one of said amplitude ranges; and d. introducing as many supplemental bits behind said significant bits as is necessary to make up said predetermined larger number of bits, the highest-ranking supplemental bit being invariably a 1, all other supplemental bits being zeroes.
Claim 2
Independent Claim
163 words
A method of re-expanding a compressed code word, derived from an original code word with a predetermined larger number of bits, into a substantial duplicate of said original code word, said compressed word including a group of significant bits preceded by an m-bit combination identfying one of several amplitude ranges of an analog signal represented by said original code word, comprising the steps of: a. separating said m-bit combination from said group of significant bits; b. prefacing said significant group with up to (2m-1) zeroes, the number n of such zeroes depending upon the numerical value of said m-bit combination; c. inserting a 1 just ahead of said group of significant bits upon said numerical value identifying any but the lowest one of said amplitude ranges; and d. introducing as many supplemental bits behind said significant bits as is necessary to make up said predetermined larger number of bits, the highest-ranking supplemental bit being invariably a 1, all other supplemental bits being zeroes.
Claim 3
Dependent Claim
44 words
A method as defined in claim 1 wherein both the original word and the compressed word include a sign bit in first position, comprising the further step of transferring said sign bit from said compressed word to a leading position in the re-expanded word.
Claim 4
Dependent Claim
20 words
A method as defined in claim 1 wherein said number n equals the difference between (2m-1) and said numerical value.
Claim 5
Independent Claim
224 words
A system for re-expanding a compressed code word, derived from an original code word with a predetermined larger number of bits, into a substantial duplicate of said original code word, said compressed word including a group of significant bits preceded by an m-bit combination identifying one of several amplitude ranges of an analog signal represented by said original code word, comprising: an input register with a number of stages sufficient to accommodate the m bits of said combination and said significant bits; an expansion register with a larger number of stages including a last stage of lowest numerical rank; circuitry between said registers for transferring said significant bits from respective stages of said input register to consecutive stages of said expansion register ahead of said last stage; logic means with input connections to stages of said input register accommodating said m bits, said logic means controlling said citcuitry for introducing a finite marking bit into a stage of said expansion register following those occupied by said significant bits, the number of stages separating the latter stages from the stage occupied by said marking bit depending upon the numerical value p of said m-bit combination; and stepping means connected to said expansion register for jointly shifting said significant bits and said markimg bit therein to lower-ranking stages until said marking bit occupies said last stage.
Claim 6
Independent Claim
224 words
A system for re-expanding a compressed code word, derived from an original code word with a predetermined larger number of bits, into a substantial duplicate of said original code word, said compressed word including a group of significant bits preceded by an m-bit combination identifying one of several amplitude ranges of an analog signal represented by said original code word, comprising: an input register with a number of stages sufficient to accommodate the m bits of said combination and said significant bits; an expansion register with a larger number of stages including a last stage of lowest numerical rank; circuitry between said registers for transferring said significant bits from respective stages of said input register to consecutive stages of said expansion register ahead of said last stage; logic means with input connections to stages of said input register accommodating said m bits, said logic means controlling said citcuitry for introducing a finite marking bit into a stage of said expansion register following those occupied by said significant bits, the number of stages separating the latter stages from the stage occupied by said marking bit depending upon the numerical value p of said m-bit combination; and stepping means connected to said expansion register for jointly shifting said significant bits and said markimg bit therein to lower-ranking stages until said marking bit occupies said last stage.
Claim 7
Dependent Claim
68 words
A system as defined in claim 4 wherein said logic means comprises a gating matrix in said circuitry responsive to the presence of at least one true signal on said input connections for introducing another finite bit into a stage of said expansion register immediately preceding the stages occupied by said significant bits for joint shifting with said significant bits and said marking bit by said stepping means.
Claim 8
Dependent Claim
50 words
A system as defined in claim 5 wherein said gating matrix is operative, in response to a numerical value p identifying any except the two lowest amplitude ranges, to introduce a further finite bit into a stage of said expansion register immediately following the stages occupied by said significant bits.
Claim 9
Dependent Claim
50 words
A system as defined in claim 4 wherein said stepping means comprises a source of clock pulses for progressively shifting the contents of said expansion register and feedback means connected to said last stage thereof for blocking said clock pulses upon arrival of said marking bit in said last stage.
Claim 10
Dependent Claim
58 words
A system as defined in claim 7, further comprising an output register with respective stages connected to the stages of said expansion register other than said last stage, and read-out means effective after operation of said stepping means for unloading the stages of said expansion register other than said last stage into corresponding stages of said output register.
Claim 11
Dependent Claim
38 words
A system as defined in claim 8, wherein said input register has an additional stage accommodating a sign bit, said output register having a corresponding stage directly connected to said additional stage for receiving said sign bit therefrom.
Claim 12
Dependent Claim
93 words
A system as defined in claim 5 wherein said gating matrix has a first output for causing the transfer of said significant bits from said input register to relatively low-ranking consecutive stages of said expansion register, in response to magnitudes of said numerical value p identifying a lower group of amplitude ranges, and a second output for causing the transfer of said significant bits from said input register to relatively high-ranking consecutive stages of said expansion register, in response to magnitudes of said numerical value p identifying a higher group of amplitude ranges.
References Cited (Backward Citations)
US3594560A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-27 | 1977-02-26 | 1977-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-27 | 1981-02-26 | 1981-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-27 | 1985-02-26 | 1985-08-28 | $7700.00 | Window Closed / Lapsed |