US4583012A
Expired / Lapsed
US
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Logical circuit array
Assignee: Arris Technology Inc
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Filing: 1983-10-20
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Granted: 1986-04-15
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Expires: 2003-10-20
Abstract
Abstract A logical circuit array is provided in which the AND and OR planes are folded together and all of the logic cell transistor gates are oriented in the same direction. The array comprises a plurality of AND rows R 0 through R n , and means for precharging the AND rows to one logic level, e.g. V DD . An additional row R a is provided along with means for precharging the additional row to another logic level, e.g., ground. The array includes a plurality of data columns and an output column coupled to AND row R 0 . A plurality of logic cells is divided among AND rows R 0 through R n-1 . Each of the logic cells has an input terminal coupled to a data column, a first output terminal connected to the AND row with which the logic cell is associated, and a second output terminal connected to the next successive AND row in the array. A plurality of logic cells is associated with AND row R n , with each such cell having an input terminal coupled to a data column, a first output terminal connected to AND row R.sub. n, and a second output terminal connected to additional row R a . In the array, the AND conditions of signals on the data columns are formed on the AND rows by the logic cells associated therewith, and the OR condition of the AND rows is formed on the output column.
Inventors
- 👤 Kent F. Smith
- 👤 Tony M. Carter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:03
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
229 words
A logical circuit array comprising: a plurality of AND rows R 0 through R n ; means for precharging said AND rows to one logic level; an additional row R a ; means for precharging said additional row to another logic level; a plurality of data columns; a plurality of logic cells divided among each of AND rows R 0 through R n-1 , each logic cell having an input terminal coupled to a data column, a first output terminal connected to the AND row with which the logic cell is associated, and a second output terminal connected to the next successive AND row in the array; a plurality of logic cells associated with AND row R n , each logic cell associated with AND row R n having an input terminal coupled to a data column, a first output terminal connected to AND row R n , and a second output terminal connected to additional row R a ; an output column coupled to AND row R 0 ; and a memory element having an input coupled to said output column and an output coupled to drive one of said data columns; whereby the AND conditions of signals on the data columns are formed on the AND rows by the logic cells associated therewith, and the OR condition of the AND rows is formed on the output column.
Claim 2
Dependent Claim
229 words
A logical circuit array comprising: a plurality of AND rows R 0 through R n ; means for precharging said AND rows to one logic level; an additional row R a ; means for precharging said additional row to another logic level; a plurality of data columns; a plurality of logic cells divided among each of AND rows R 0 through R n-1 , each logic cell having an input terminal coupled to a data column, a first output terminal connected to the AND row with which the logic cell is associated, and a second output terminal connected to the next successive AND row in the array; a plurality of logic cells associated with AND row R n , each logic cell associated with AND row R n having an input terminal coupled to a data column, a first output terminal connected to AND row R n , and a second output terminal connected to additional row R a ; an output column coupled to AND row R 0 ; and a memory element having an input coupled to said output column and an output coupled to drive one of said data columns; whereby the AND conditions of signals on the data columns are formed on the AND rows by the logic cells associated therewith, and the OR condition of the AND rows is formed on the output column.
Claim 3
Dependent Claim
60 words
The array of claim 1 further comprising: additional groups of AND rows with associated logic cells; means for precharging said additional AND rows to said one logic level; means for coupling the first row of each additional group to an output column; and means for coupling the last row of each additional group to said additional row R a .
Claim 4
Dependent Claim
45 words
The array of claim 1 wherein said means for precharging said AND rows operates during a first time period in response to a first clock pulse; and said means for precharging said additional row operates during a second time period after said first time period.
Claim 5
Dependent Claim
23 words
The array of claim 1 wherein said AND rows are precharged to a logical high, and said additional row is precharged to ground.
Claim 6
Independent Claim
169 words
A method for processing data in a logic array comprising the steps of: precharging a plurality of AND rows to one logic level; precharging an additional row to another logic level; arranging a plurality of logic cells in each AND row to form on each respective AND row the AND condition of data from a plurality of data columns driving the logic cells in that AND row; coupling said AND rows and said additional row together through said logic cells; rippling the logic level of said additional row through said logic cells to successive AND rows to form the OR condition of all of said AND rows on the AND row coupled most remotely to said additional row; reading the OR condition of said AND rows from an OR column coupled to the AND row which is most remotely coupled to said additional row; and driving at least one of said data columns with data output from a memory element which has an input coupled to said OR column.
Claim 7
Independent Claim
169 words
A method for processing data in a logic array comprising the steps of: precharging a plurality of AND rows to one logic level; precharging an additional row to another logic level; arranging a plurality of logic cells in each AND row to form on each respective AND row the AND condition of data from a plurality of data columns driving the logic cells in that AND row; coupling said AND rows and said additional row together through said logic cells; rippling the logic level of said additional row through said logic cells to successive AND rows to form the OR condition of all of said AND rows on the AND row coupled most remotely to said additional row; reading the OR condition of said AND rows from an OR column coupled to the AND row which is most remotely coupled to said additional row; and driving at least one of said data columns with data output from a memory element which has an input coupled to said OR column.
Claim 8
Dependent Claim
23 words
The method of claim 5 wherein said additional row is precharged to ground, and said AND rows are precharged to a logical high.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |