Patent US4583009A successfully refreshed from Google Patents.
US4583009A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Precision voltage reference for systems such as analog to digital converters
Assignee: Fluke Corp
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Filing: 1983-11-14
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Granted: 1986-04-15
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Expires: 2003-11-14
Abstract
Abstract The ladder network of a recirculation of remainder analog to digital converter has a voltage source that is regulated by a transistor and Zener diode together with feedback circuitry responsive to the regulated output voltage. Current through the circuit is controlled by feedback to establish equal and opposite temperature coefficients in the transistor and Zener diode of the regulator. The temperature stabilized voltage regulator produced thereby eliminates any requirement for trimmer potentiometers.
Inventors
- 👤 Benjamin Eng, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:35
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/18; G05F1/00; G05F1/10; G05F1/46; G05F1/56; H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/40; H03M1/403; Y; Y10; Y10S; Y10S323/00; Y10S323/907
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
275 words
A circuit for developing first and second reference sources for analog to digital converters or other electrical systems, comprising: a transistor means having a control electrode and a pair of output electrodes, the transistor means having a negative temperature coefficient; a reference diode means having a positive temperature coefficient and connected in series with one of said output electrodes of said transistor means, the temperature coefficients of said transistor means and said reference diode means being equal in magnitude at a predetermined magnitude of current flowing therethrough; first and second operational amplifiers each having inverting input, non-inverting input and output terminals, the output terminal of said first operational amplifier establishing a first reference source; a first signal path established between the inverting input terminal of said second operational amplifier and said first reference source; a second signal path established between said first reference source and a junction between said transistor means and said reference diode means; the non-inverting input terminal of said second operational amplifier being connected to the ground; the output terminal of said second operational amplifier establishing a second reference source; a first resistor connected between said second reference source and the other of said output electrodes of said transistor means and having a resistance value sufficient to establish the predetermined current magnitude; the inverting and non-inverting input terminals of said first operational amplifier being connected respectively, to a junction between said first resistor and said transistor means and to the ground; and a precision resistance divider means connected between said first reference source and the ground; an output of said divider means being applied to the control electrode of said transistor means.
Claim 2
Dependent Claim
275 words
A circuit for developing first and second reference sources for analog to digital converters or other electrical systems, comprising: a transistor means having a control electrode and a pair of output electrodes, the transistor means having a negative temperature coefficient; a reference diode means having a positive temperature coefficient and connected in series with one of said output electrodes of said transistor means, the temperature coefficients of said transistor means and said reference diode means being equal in magnitude at a predetermined magnitude of current flowing therethrough; first and second operational amplifiers each having inverting input, non-inverting input and output terminals, the output terminal of said first operational amplifier establishing a first reference source; a first signal path established between the inverting input terminal of said second operational amplifier and said first reference source; a second signal path established between said first reference source and a junction between said transistor means and said reference diode means; the non-inverting input terminal of said second operational amplifier being connected to the ground; the output terminal of said second operational amplifier establishing a second reference source; a first resistor connected between said second reference source and the other of said output electrodes of said transistor means and having a resistance value sufficient to establish the predetermined current magnitude; the inverting and non-inverting input terminals of said first operational amplifier being connected respectively, to a junction between said first resistor and said transistor means and to the ground; and a precision resistance divider means connected between said first reference source and the ground; an output of said divider means being applied to the control electrode of said transistor means.
Claim 3
Dependent Claim
14 words
The circuit of claim 1, including a second resistor in said second signal path.
Claim 4
Dependent Claim
29 words
The circuit of claim 1, including diode clamping circuit means at the output terminal of said first operational amplifier to limit the magnitude of said first level reference source.
Claim 5
Dependent Claim
17 words
The circuit of claim 1, wherein said first and second level reference sources have, respectively, opposite polarities.
Claim 6
Dependent Claim
14 words
The circuit of claim 1, wherein said reference diode means is a Zener diode.
Claim 7
Dependent Claim
54 words
The circuit of claim 1, wherein said control and output electrodes of transistor means comprise emitter, base and collector terminals, the base terminal being connected to said divider means, the collector terminal being connected to said first resistor and the emitter terminal being connected to said reference diode means and to said second resistor.
Claim 8
Dependent Claim
27 words
The circuit of claim 2, including a third resistor connected between said second level reference source and the junction between the transistor and the reference diode means.
Claim 9
Dependent Claim
24 words
The circuit of claim 1, wherein the first and second reference sources are connected across a ladder network of a digital to analog converter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |