US4581548A
Expired / Lapsed
US
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Address decoder
Assignee: Intersil Corp
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Filing: 1983-03-15
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Granted: 1986-04-08
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Expires: 2003-03-15
Abstract
Abstract An address decoder architecture capable of having a precharge signal for the word line coincident with the enabling of the decoder section to reduce the operating cycle. The word line latch is separate and distinct from the word line driver such that disablement of the word line driver during readdressing of the enabled decoder will not effect the portion of the cycle that the word line maintains its logic state.
Inventors
- 👤 William R. Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:03
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; G11C8/08; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
141 words
An address decoder comprising: decoder means for decoding address signals and providing a decoded signal in response to a decoder enable signal; line driver means for driving a line in response to said decoded signal and driver enable signal and for isolating said line from said line decoder means during a latch period in response to a lack of a driver enable signal which disables said line driver means; latch means for latching said line to the value established on the line by said line driver means in response to a latch enable signal during said latch period; precharge means for precharging said line in response to a precharge signal distinct from said decoder enable signal during a precharge period; and signal means for generating said decoder enable signal, said driver enable signal, said latch enable signal and said precharge signal.
Claim 2
Dependent Claim
141 words
An address decoder comprising: decoder means for decoding address signals and providing a decoded signal in response to a decoder enable signal; line driver means for driving a line in response to said decoded signal and driver enable signal and for isolating said line from said line decoder means during a latch period in response to a lack of a driver enable signal which disables said line driver means; latch means for latching said line to the value established on the line by said line driver means in response to a latch enable signal during said latch period; precharge means for precharging said line in response to a precharge signal distinct from said decoder enable signal during a precharge period; and signal means for generating said decoder enable signal, said driver enable signal, said latch enable signal and said precharge signal.
Claim 3
Dependent Claim
31 words
An address decoder according to claim 1, wherein said signal means generates said precharge signal as a logic high during a period when said decoder enable signal is a logic high.
Claim 4
Dependent Claim
33 words
An address decoder according to claim 2, wherein said signal means generates said driver enable signal as a logic low and said latch enable signal as a logic low during said precharge period.
Claim 5
Dependent Claim
24 words
An address decoder according to claim 2, wherein said signal means generates said decoder enable signal as a logic low during said latch period.
Claim 6
Dependent Claim
33 words
An address decoder according to claim 1 wherein said signal means generates said driver enable signal as a logic low and said latch enable signal as a logic low during said precharge period.
Claim 7
Dependent Claim
40 words
An address decoder according to claim 5 wherein said signal means generates said decoder enable signal as a logic low during a portion of said latch period and as a logic high preceeding, during and subsequent to said precharge period.
Claim 8
Dependent Claim
24 words
An address decoder according to claim 1, wherein said signal means generates said decoder enable signal as a logic low during said latch period.
Claim 9
Dependent Claim
25 words
An address decoder according to claim 1 wherein said signal means generates said driver enable signal a delay period after generating said latch enable signal.
Claim 10
Dependent Claim
43 words
An address decoder according to claim 1 wherein said line has first and second ends and said precharge means include a pair of precharge means one coupled to each end of said line for precharging said line in response to said precharge signal.
Claim 11
Dependent Claim
34 words
An address decoder according to claim 9, wherein said line driver means is coupled to said first end of said line and said latch means is coupled to said second end of said line.
Claim 12
Dependent Claim
94 words
An address decoder according to claim 1, wherein said latch means include a first inverter means having an input connected to said line and an output and a second gated inverter means having an input connected to the output of said first inverter means, an output connected to said line, and a gate for receiving said latch enable signal; and wherein said line driver means includes a third gated inverter means having an input connected to said decoder means, an output connected to said line, and a gate for receiving said driver enable signal.
Claim 13
Dependent Claim
120 words
An address decoder comprising: decoder means having an address input and an enable input for generating a line select signal in response to an address signal and a decoder enable signal; line driver means having a line select input and an enable input for generating a line drive signal on a line in response to said line select signal and a driver enable signal distinct from said decoder enable signal; precharge means for precharging said line in response to a precharge signal distinct from said decoder enable signal; latch means connected to said line for latching said line with said line drive signal; and signal means for generating said decoder enable signal, said driver enable signal and said precharge signal.
Claim 14
Dependent Claim
120 words
An address decoder comprising: decoder means having an address input and an enable input for generating a line select signal in response to an address signal and a decoder enable signal; line driver means having a line select input and an enable input for generating a line drive signal on a line in response to said line select signal and a driver enable signal distinct from said decoder enable signal; precharge means for precharging said line in response to a precharge signal distinct from said decoder enable signal; latch means connected to said line for latching said line with said line drive signal; and signal means for generating said decoder enable signal, said driver enable signal and said precharge signal.
Claim 15
Dependent Claim
33 words
An address decoder according to claim 12, wherein said line has first and second ends and said precharge means includes a pair of precharge means, one connected to each end of said line.
Claim 16
Dependent Claim
28 words
An address decoder according to claim 13, wherein said line driver means and said latch means are connected to said first and second ends of said line respectively.
Claim 17
Dependent Claim
89 words
An address decoder according to claim 13, wherein said line driver means includes a complementary field effect transistor inverter whose input is said line select signal and whose output is said line drive signal, and enable P channel device in series with a P channel device of said CFET inverter with its gate receiving the inverse of said driver enable signal and an enable N channel device in series with an N channel device of said CFET inverter with its gate receiving the inverse of said latch enable signal.
Claim 18
Dependent Claim
33 words
An address decoder according to claim 15, wherein said enable N and P channel devices are between said CFET inverter's N and P channel devices respectively and said output of said CFET inverter.
Claim 19
Dependent Claim
36 words
An address decoder according to claim 13 wherein said latch means is responsive to a latch enable signal for latching said line with said line drive signal; and said signal means generates said latch enable signal.
Claim 20
Dependent Claim
84 words
An address decoder according to claim 17, wherein said line driver means includes a complementary field effect transistor inverter whose input is said line select signal and whose output is said line drive signal, an enable P channel device in series with a P channel device of said inverter with its gate receiveing said driver enable signal and an enable N channel device in series with an N channel device of said inverter with its gate receiving the inverse of said latch enable signal.
Claim 21
Dependent Claim
110 words
An address decoder according to claim 17, wherein said latch means includes a first complementary field effect transistor inverter whose input is connected to said line and a second CFET inverter whose input is connected to the output of said first CFET inverter and whose output is connected to said line; said second CFET inverter includes an enable P channel device in series with a P channel device of said second CFET inverter with its gate receiving the inverse of said latch enable signal and an enable N channel device in series with an N channel device of said second CFET inverter with its gate receiving said latch enable signal.
Claim 22
Dependent Claim
106 words
An address decoder according to claim 17, wherein said latch means includes a first complementary field effect transistor inverter whose input is connected to said line and a second CFET inverter whose input is connected to the output of said first CFET inverter and whose output is connected to said line; said second CFET inverter includes an enable P channel device in series with a P channel device of said second CFET inverter with its gate receiving said precharge signal and an enable N channel device in series with an N channel device of said second CFET inverter with its gate receiving said latch enable signal.
Claim 23
Dependent Claim
29 words
An address decoder according to claim 17 wherein said signal means generates a logic low driver and latch enable signal during the period of a logic high precharge signal.
Claim 24
Dependent Claim
28 words
An address decoder according to claim 21 wherein said signal means generates a logic low driver enable signal during the period of a logic high latch enable signal.
Claim 25
Dependent Claim
35 words
An address decoder according to claim 21 wherein said signal means generates a logic low decoder enable signal during the period of a simultaneous logic low driver enable signal and logic high latch enable signal.
Claim 26
Dependent Claim
27 words
An address decoder according to claim 12 wherein said signal means generates a logic high precharge signal during the period of a logic high decoder enable signal.
Claim 27
Dependent Claim
28 words
An address decoder according to claim 24 wherein said signal means generates a logic low drive enable signal for the duration of a logic low decoder enable signal.
Claim 28
Dependent Claim
28 words
An address decoder according to claim 25 wherein said signal means also generates a logic low driver enable signal for the duration of a logic high precharge signal.
References Cited (Backward Citations)
US4086500A
Cited
US4275312A
Cited
US4281399A
Cited
US4216389A
Cited
US4289982A
Cited
US4305139A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-07 | 1989-10-07 | 1990-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-07 | 1993-10-07 | 1994-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-07 | 1997-10-07 | 1998-04-08 | $7700.00 | Window Closed / Lapsed |