US4580278A
Expired / Lapsed
US
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Read clock producing system
Assignee: Sansui Electric Co Ltd
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Filing: 1983-10-25
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Granted: 1986-04-01
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Expires: 2003-10-25
Abstract
Abstract In a read clock producing system for generating a read clock signal which is used for extracting a digital information portion of a digital coded signal, the system comprises means for delaying a pulse obtained by comparing data with a certain threshold level, means for generating a clock pulse having a pulse width proportional to the delay, said generating means including a frequency division circuit, flip-flop and EOR means for comparing the pulse width with a predetermined pulse width, a differential amplifier for comparing the data with a second threshold level adapted to change in accordance with the above comparison, and the control means for controlling the delay by the use of an output from said comparison.
Inventors
- 👤 Takaaki Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:13
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
282 words
In a read clock producing system for generating a read clock signal which is used for deciding and extracting a digital information portion of a digital coded signal in case of decoding original digital information from a transmission signal that is delivered from a transmission system for transmitting the digital coded signal including a synchronizing signal; a read clock producing system comprising source clock generating means (2, 5) for generating a source clock signal at a frequency integral times that of the required read clock signal by the use of a phase-lock loop based on the synchronizing signal in the transmission signal, clock generation means (6) conneted to the output of said source clock generation means for dividing, the frequency of the source clock signal by means of a frequency division counter so as to generate a clock signal at a frequency equal to a bit rate of the digital information portion, a resetting means (7, 8) having its output connected to said clock generation means, for detecting a timing at which the transmission signal traverses a threshold level at a leading edge of a first digital information signal succeeding the synchronizing signal in the transmission signal, so as to reset said frequency division counter at a time of the detection, and level control means (9-16), having its input connected to the output of said clock generation means and having its outupt connected to the input of said resetting means for detecting a phase difference between the digital information signal in the transmission signal and the read clock generated by said clock generation means and for variably controlling the threshold level of said resetting means so as to decrease the phase difference.
Claim 2
Dependent Claim
282 words
In a read clock producing system for generating a read clock signal which is used for deciding and extracting a digital information portion of a digital coded signal in case of decoding original digital information from a transmission signal that is delivered from a transmission system for transmitting the digital coded signal including a synchronizing signal; a read clock producing system comprising source clock generating means (2, 5) for generating a source clock signal at a frequency integral times that of the required read clock signal by the use of a phase-lock loop based on the synchronizing signal in the transmission signal, clock generation means (6) conneted to the output of said source clock generation means for dividing, the frequency of the source clock signal by means of a frequency division counter so as to generate a clock signal at a frequency equal to a bit rate of the digital information portion, a resetting means (7, 8) having its output connected to said clock generation means, for detecting a timing at which the transmission signal traverses a threshold level at a leading edge of a first digital information signal succeeding the synchronizing signal in the transmission signal, so as to reset said frequency division counter at a time of the detection, and level control means (9-16), having its input connected to the output of said clock generation means and having its outupt connected to the input of said resetting means for detecting a phase difference between the digital information signal in the transmission signal and the read clock generated by said clock generation means and for variably controlling the threshold level of said resetting means so as to decrease the phase difference.
Claim 3
Dependent Claim
118 words
A read clock producing system comprising means for delaying a pulse obtained by comparing data with a certain threshold level, means (6, 10), connected to the output of said delaying means, for generating a pulse having a pulse width proportional to the delay, means (12-15), connected to the output of said pulse generating means, for comparing the pulse width with a predetermined pulse width, and comparison means (7), connected to the output of said pulse width comparing means, for comparing the data with a second threshold level adapted to change in accordance with the output of said pulse width comparing means, wherein the delay caused by said delaying means is controlled by the output from said comparison means.
Claim 4
Dependent Claim
118 words
A read clock producing system comprising means for delaying a pulse obtained by comparing data with a certain threshold level, means (6, 10), connected to the output of said delaying means, for generating a pulse having a pulse width proportional to the delay, means (12-15), connected to the output of said pulse generating means, for comparing the pulse width with a predetermined pulse width, and comparison means (7), connected to the output of said pulse width comparing means, for comparing the data with a second threshold level adapted to change in accordance with the output of said pulse width comparing means, wherein the delay caused by said delaying means is controlled by the output from said comparison means.
Claim 5
Dependent Claim
156 words
A read clock producing system according to claim 1, wherein said level control means comprises a comparator (9) which compares a fixed threshold level and data, a first flip-flop (10) which sets an output of said comparator in accordance with the frequency-divided clock signal, first exclusive OR means (13) for taking an EOR between an output of said first flip-flop and the output of said comparator and delivering a pulse width proportional to an amount of deviation of the threshold level, a second flip-flop (12) which sets the output of said first flip-flop in accordance with an inverted signal of the output of said frequency division counter, and second exclusive OR means (14) for taking an EOR between an output of said second flip-flop and the output of said first flip-flop and delivering a reference pulse width, whereby the threshold level is changed in correspondence with the timing of the resetting of said frequency division counter.
Claim 6
Dependent Claim
40 words
A read clock producing system according to claim 3 wherein said level control meansincludes a second comparator (15) for comparing the outputs of the first and second EOR's and an integrator (16) connected to the output of the second comparator.
Claim 7
Dependent Claim
98 words
A read clock producing system according to claim 3 wherein said level control means includes a second comparator (15) for comparing the outputs of the first and second EOR's, an integrator (16) connected to the output of the second comparator, a switch (17) connected to the output of the comparator and controlled to turn to "off" when the output of the integrator becomes "0" and a capacitor (18) connected to the switch for storing an optimum threshold level when the switch is off and for being charged by the output of the integrator when the switch is on.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-31 | 1989-09-30 | 1990-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-31 | 1993-09-30 | 1994-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-31 | 1997-09-30 | 1998-04-01 | $7700.00 | Window Closed / Lapsed |