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US4575815A Expired / Lapsed US ⏱️ 0.0 years remaining

Data storage unit

Assignee: Fujitsu Services Ltd
•
Filing: 1985-08-01
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Granted: 1986-03-11
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Expires: 2005-08-01
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Abstract

Abstract In a data storage unit, internal timing signals are produced by scanning a writable control memory. Thus, the timing of the storage unit can easily be varied, simply by re-writing the contents of the control memory. This allows the use of a faster clock rate without the necessity for complete redesign of the storage unit. The basic clock period is sub-divided into a number of sub-periods, allowing the timing signals to be adjusted with an accuracy better than one clock period.

Inventors

  • 👤 Stephen J. Delahunt

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 14:51
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 204 words
A data storage unit having timing control means for producing internal timing signals for the unit on a plurality of timing signal lines, the timing control means comprising: (a) a writable control memory having a plurality of individually addressed locations, each location containing a word having a plurality of bits each bit corresponding respectively to each of said plurality of timing signal lines, (b) means for generating a sequence of clock signals, (c) means responsive to the sequence of clock signals for addressing the locations of the control memory sequentially to read out the words from successive locations in successive clock signals, (d) means connected to said clock signals generating means for producing a plurality of further clock signals sub-dividing each of said clock signal into a plurality of sub-clock signals, (e) means connected to said further clock signals producing means for selecting one of the further clock signals for each timing signal line, and (f) gating means responsive to the selected further clock signals and to each word out of the control memory, for producing a timing signal on each said timing signal line whenever the corresponding bit of the word read out of the control memory is set to a predetermined value.
Claim 2
Dependent Claim 204 words
A data storage unit having timing control means for producing internal timing signals for the unit on a plurality of timing signal lines, the timing control means comprising: (a) a writable control memory having a plurality of individually addressed locations, each location containing a word having a plurality of bits each bit corresponding respectively to each of said plurality of timing signal lines, (b) means for generating a sequence of clock signals, (c) means responsive to the sequence of clock signals for addressing the locations of the control memory sequentially to read out the words from successive locations in successive clock signals, (d) means connected to said clock signals generating means for producing a plurality of further clock signals sub-dividing each of said clock signal into a plurality of sub-clock signals, (e) means connected to said further clock signals producing means for selecting one of the further clock signals for each timing signal line, and (f) gating means responsive to the selected further clock signals and to each word out of the control memory, for producing a timing signal on each said timing signal line whenever the corresponding bit of the word read out of the control memory is set to a predetermined value.
Claim 3
Dependent Claim 31 words
A data storage unit according to claim 1 wherein the means for producing the plurality of further clock signals comprises a shift register connected to receive shift pulses from an oscillator.
Claim 4
Dependent Claim 37 words
A data storage unit according to claim 1, including data input and output registers, and at least one address register, wherein said internal timing signals include gating signals for controlling the loading of information into those registers.
Claim 5
Dependent Claim 35 words
A data storage unit according to claim 3 further including a Hamming code register, wherein said internal timing signals further include a gating signal for controlling the loading of a Hamming code into that register.

References Cited (Backward Citations)

US3443070A Cited
US3866022A Cited
US4063308A Cited
US4095265A Cited
US4122309A Cited
US4165490A Cited
US4257108A Cited
US4321687A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-03-10 1989-09-09 1990-03-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-03-10 1993-09-09 1994-03-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-03-10 1997-09-09 1998-03-11 $7700.00 Window Closed / Lapsed

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