System for generating timing and control signals

Claim 1

A system comprising: clock means for providing a succession of clock pulses of equal clock pulse intervals, each sequence of M clock pulse intervals defining a data frame, M being an integer other than a distinct prime and not less than one thousand; a plurality of modulo-mi multistage counters where each mi is a different prime power divisor of M, each modulo-mi counter comprising a different cascade of Alpha modulo-pi counters, where pi in each cascade is the same and is a different distinct prime of M and Alpha i in each cascade is an integer not less than 1, with at least one Alpha i being greater than 1 and each mi pi ; means for coupling said counters to said clock means for clocking said modulo-mi counters in parallel with said clock pulses, with the first counter in each cascade being clocked directly with each clock pulse and each succeeding counter in a cascade is clocked by a clock pulse only when the preceding counter in a cascade changes from a last state in its state cycle to a first state in its cycle whereby each modulo-pi counter cycles through a cycle of pi states and the combined states of the Alpha i counters forming each modulo-mi counter represent different states of a state cycle of mi states; and logic means coupled to selected ones of said counters for providing a plurality of subperiods of said data frame as a function of the states of the counters to which it is cOupled, each subperiod being a sequence of output pulses, each with an output pulse interval which is equal to the clock pulse interval times a different factor definable as Xi, where Xi is an integer and a factor of M and wherein the smallest value of Xi is equal to the smallest distinct prime of M, said subperiods including one delayed subperiod whose first output pulse is delayed by an interval from the start of said data frame, which is not less than one clock pulse interval and not greater than Y clock pulse intervals, where Y < OR = Xi - 1.

Claim 2

A system comprising: clock means for providing a succession of clock pulses of equal clock pulse intervals, each sequence of M clock pulse intervals defining a data frame, M being an integer other than a distinct prime and not less than one thousand; a plurality of modulo-mi multistage counters where each mi is a different prime power divisor of M, each modulo-mi counter comprising a different cascade of Alpha modulo-pi counters, where pi in each cascade is the same and is a different distinct prime of M and Alpha i in each cascade is an integer not less than 1, with at least one Alpha i being greater than 1 and each mi pi ; means for coupling said counters to said clock means for clocking said modulo-mi counters in parallel with said clock pulses, with the first counter in each cascade being clocked directly with each clock pulse and each succeeding counter in a cascade is clocked by a clock pulse only when the preceding counter in a cascade changes from a last state in its state cycle to a first state in its cycle whereby each modulo-pi counter cycles through a cycle of pi states and the combined states of the Alpha i counters forming each modulo-mi counter represent different states of a state cycle of mi states; and logic means coupled to selected ones of said counters for providing a plurality of subperiods of said data frame as a function of the states of the counters to which it is cOupled, each subperiod being a sequence of output pulses, each with an output pulse interval which is equal to the clock pulse interval times a different factor definable as Xi, where Xi is an integer and a factor of M and wherein the smallest value of Xi is equal to the smallest distinct prime of M, said subperiods including one delayed subperiod whose first output pulse is delayed by an interval from the start of said data frame, which is not less than one clock pulse interval and not greater than Y clock pulse intervals, where Y < OR = Xi - 1.

Claim 10

A method for producing a selected output pulse related to a data frame represented by M clock pulse intervals of a succession of M equal interval clock pulses, M being an integer not less than one thousand and other than a distinct prime and is equal to the product of n prime power factors definable as m1 through mn, where n is at least equal to 2, the steps comprising: providing a first cascade of Alpha 1 modulo-p1 counters where m1 p1 , p1 being a distinct prime and being the same in each counter of said first cascade and Alpha 1 is an integer greater than 1; providing at least a second cascade of Alpha 2 modulo-p2 counters where m2 p2 , p2 being a distinct prime different from p1 and the same in each counter of said second cascade and Alpha 2 is an integer greater than 1; clocking said first and second cascades of counters with equal interval clock pulses, with the first counter in each cascade being clocked directly by each clock pulse and each preceding counter in a cascade being clocked by a clock pulse only when the preceding counter in the cascade changes from the last state in its state cycle to the first state in its cycle, whereby each modulo-p1 counter cycles through a cycle of p1 states, with the combined states of said Alpha 1 modulo-p1 counters representing a cycle of m1 states, and each modulo-p2 counter cycles through a cycle of p2 states with the combined states of said Alpha 2 modulo-p2 counters representing a cycle of m2 states; and utilizing the states of selected stages of all of said counters to provide a selected output pulse during each data frame, at a time from the start of said data frame which is an integer multiple of said clock pulse interval.

Claim 11

A method for producing a selected output pulse related to a data frame represented by M clock pulse intervals of a succession of M equal interval clock pulses, M being an integer not less than one thousand and other than a distinct prime and is equal to the product of n prime power factors definable as m1 through mn, where n is at least equal to 2, the steps comprising: providing a first cascade of Alpha 1 modulo-p1 counters where m1 p1 , p1 being a distinct prime and being the same in each counter of said first cascade and Alpha 1 is an integer greater than 1; providing at least a second cascade of Alpha 2 modulo-p2 counters where m2 p2 , p2 being a distinct prime different from p1 and the same in each counter of said second cascade and Alpha 2 is an integer greater than 1; clocking said first and second cascades of counters with equal interval clock pulses, with the first counter in each cascade being clocked directly by each clock pulse and each preceding counter in a cascade being clocked by a clock pulse only when the preceding counter in the cascade changes from the last state in its state cycle to the first state in its cycle, whereby each modulo-p1 counter cycles through a cycle of p1 states, with the combined states of said Alpha 1 modulo-p1 counters representing a cycle of m1 states, and each modulo-p2 counter cycles through a cycle of p2 states with the combined states of said Alpha 2 modulo-p2 counters representing a cycle of m2 states; and utilizing the states of selected stages of all of said counters to provide a selected output pulse during each data frame, at a time from the start of said data frame which is an integer multiple of said clock pulse interval.