US4573141A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory interface for communicating between two storage media having incompatible data formats
Assignee: General Electric Co
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Filing: 1984-04-12
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Granted: 1986-02-25
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Expires: 2004-04-12
Abstract
Abstract An electronic demand register for an electric meter includes a volatile storage for normal processing of data and a non-volatile storage into which data is serially written upon the occurrence of conditions which may threaten the integrity of such data and from which the data is again retrieved when the condition no longer exists. The data formats for transmission of the data to the non-volatile memory and for receiving it therefrom do not agree with the data formats which the volatile storage must have. A communications buffer assembles a data package for transmission to the non-volatile memory which has a format which can be suitably serially transmitted to the non-volatile memory and be properly interpreted there due to the manner in which the non-volatile memory recognizes and stores data. In addition, the communications buffer receives the serial data from the non-volatile memory and, by left shift and selection of only valid portions of the data, assembles data suitable for transmission to the volatile memory.
Inventors
- 👤 Francois Y. Simon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:42
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1441; G01; G01R; G01R21/00; G01R21/133; G01R21/1333; G01R21/1338; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
245 words
Apparatus for communicating between a first memory capable of sending and receiving first data words having a first number of bits and a second memory capable of sending and receiving second data words having a second number of bits wherein neither of said first or said second numbers of bits is evenly divisible by the other thereof, comprising: means for assembling a first predetermined number of said first data words into a first data block; means for appending a leading word to said first data block; means for serially transmitting said leading word and said first data block to said second memory; said leading word including a pattern of bits which are at least partly ignored by said second memory and a remainder of said leading word, together with said first data block, forming said second data word whereby said second memory is effective to receive data from said first memory; means for serially receiving a second predetermined number of said second words from said second memory; means for forming said second predetermined number of said second words into a second data block; means for performing one of a shift and a selective transfer on said second predetermined number of said second words whereby said second words in said second data block are converted to a third data block, said third data block being a third predetermined number of said first data words; and means for communicating said third data block to said first memory.
Claim 2
Dependent Claim
245 words
Apparatus for communicating between a first memory capable of sending and receiving first data words having a first number of bits and a second memory capable of sending and receiving second data words having a second number of bits wherein neither of said first or said second numbers of bits is evenly divisible by the other thereof, comprising: means for assembling a first predetermined number of said first data words into a first data block; means for appending a leading word to said first data block; means for serially transmitting said leading word and said first data block to said second memory; said leading word including a pattern of bits which are at least partly ignored by said second memory and a remainder of said leading word, together with said first data block, forming said second data word whereby said second memory is effective to receive data from said first memory; means for serially receiving a second predetermined number of said second words from said second memory; means for forming said second predetermined number of said second words into a second data block; means for performing one of a shift and a selective transfer on said second predetermined number of said second words whereby said second words in said second data block are converted to a third data block, said third data block being a third predetermined number of said first data words; and means for communicating said third data block to said first memory.
Claim 3
Independent Claim
232 words
A method for communicating between a first memory capable of sending and receiving first data words having a first number of bits and a second memory capable of sending and receiving second data words having a second number of bits wherein neither of said first or said second numbers of bits is evenly divisible by the other thereof, comprising: assembling a first predetermined number of said first data words into a first data block; appending a leading word to said first data block; serially transmitting said leading word and said first data block to said second memory; said leading word including a pattern of bits which are at least partly ignored by said second memory and a remainder of said leading word, together with said first data block, forming said second data word whereby said second memory is effective to receive data from said first memory; serially receiving a second predetermined number of said second words from said second memory; forming said second predetermined number of said second words into a second data block; performing one of a shift and a selective transfer on said second predetermined number of said second words whereby said second words in said second data block are converted to a third data block, said third data block being a third predetermined number of said first data words; and communicating said third data block to said first memory.
Claim 4
Independent Claim
232 words
A method for communicating between a first memory capable of sending and receiving first data words having a first number of bits and a second memory capable of sending and receiving second data words having a second number of bits wherein neither of said first or said second numbers of bits is evenly divisible by the other thereof, comprising: assembling a first predetermined number of said first data words into a first data block; appending a leading word to said first data block; serially transmitting said leading word and said first data block to said second memory; said leading word including a pattern of bits which are at least partly ignored by said second memory and a remainder of said leading word, together with said first data block, forming said second data word whereby said second memory is effective to receive data from said first memory; serially receiving a second predetermined number of said second words from said second memory; forming said second predetermined number of said second words into a second data block; performing one of a shift and a selective transfer on said second predetermined number of said second words whereby said second words in said second data block are converted to a third data block, said third data block being a third predetermined number of said first data words; and communicating said third data block to said first memory.
Claim 5
Dependent Claim
253 words
A data communications system comprising: a communications buffer; a serial input/output interface; said communications buffer including means for communicating data to and from a main memory and for communicating said data to and from said serial input/output interface; said serial input/output interface including means for serially communicating fixed-length data words to a non-volatile memory and for serially receiving data words from said non-volatile memory; said non-volatile memory being of a type which requires an input data format and an output data format which includes a number of bits which is not evenly divisible into or by a number of bits in said fixed-length data words; said communications buffer including means for forming a data package for transmission through said serial input/output interface to said non-volatile memory, said data package including a leading data word appended to said data from said main memory, said leading data word including a first portion which is ignored by said non-volatile memory and a second portion which is recognized by said non-volatile memory, a combination of said second portion and said data forming said input data format compatible with said non-volatile memory; said communications buffer including means for forming a second data block of data which has been serially received from said non-volatile memory; and said communications buffer further including means for performing at least one of a shift and a selective transfer on said second data block whereby said second data block is converted to a third data block having a format compatible with said main memory.
Claim 6
Dependent Claim
253 words
A data communications system comprising: a communications buffer; a serial input/output interface; said communications buffer including means for communicating data to and from a main memory and for communicating said data to and from said serial input/output interface; said serial input/output interface including means for serially communicating fixed-length data words to a non-volatile memory and for serially receiving data words from said non-volatile memory; said non-volatile memory being of a type which requires an input data format and an output data format which includes a number of bits which is not evenly divisible into or by a number of bits in said fixed-length data words; said communications buffer including means for forming a data package for transmission through said serial input/output interface to said non-volatile memory, said data package including a leading data word appended to said data from said main memory, said leading data word including a first portion which is ignored by said non-volatile memory and a second portion which is recognized by said non-volatile memory, a combination of said second portion and said data forming said input data format compatible with said non-volatile memory; said communications buffer including means for forming a second data block of data which has been serially received from said non-volatile memory; and said communications buffer further including means for performing at least one of a shift and a selective transfer on said second data block whereby said second data block is converted to a third data block having a format compatible with said main memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-24 | 1989-08-26 | 1990-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-24 | 1993-08-26 | 1994-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-24 | 1997-08-26 | 1998-02-25 | $7700.00 | Window Closed / Lapsed |