US4571505A — Method and apparatus of reducing latch-up suscept…

Claim 1

Independent Claim 40 words

A method of using an on chip substrate bias voltage generator to control latch-up in a CMOS circuit on a substrate comprising operating the CMOS circuit, and biasing the substrate during normal circuit operation with said substrate bias voltage generator.

Claim 2

Independent Claim 40 words

A method of using an on chip substrate bias voltage generator to control latch-up in a CMOS circuit on a substrate comprising operating the CMOS circuit, and biasing the substrate during normal circuit operation with said substrate bias voltage generator.

Claim 3

Dependent Claim 48 words

The method of claim 1 including: providing a substrate to ground capacitance substantially greater than the normal parasitic capacitance; sensing a power supply transition; clamping the substrate to a known potential in response to sensing said power supply transition; and releasing said clamping after said power supply transition.

Claim 4

Dependent Claim 42 words

The method of claim 2 wherein said biasing step comprises coupling a substrate bias voltage generator to the CMOS substrate, the method further including: detecting when the substrate potential reaches a predetermined point; and inhibiting said clamping in response to said detecting.

Claim 5

Dependent Claim 61 words

The method of claim 2 wherein said method includes: sensing a power supply transition; clamping the substrate to ground in response to said sensing; determining when said power supply transition has ended; releasing said clamping in response to said determining; and pumping charge with respect to said substrate whereby except during power supply transitions, the substrate becomes biased to control latch-up.

Claim 6

Dependent Claim 44 words

The method of claim 4 further including: detecting when pumping charge with respect to said substrate causes the substrate to reach a predetermined potential; and inhibiting said clamping in response to said detecting, whereby said clamping does not occur except during power supply transitions.

Claim 7

Independent Claim 40 words

A method for controlling latch-up in a CMOS circuit on a substrate comprising the steps of: sensing a power supply transition; clamping the substrate to a known potential in response to said sensing; and releasing said clamping after said transition.

Claim 8

Independent Claim 40 words

A method for controlling latch-up in a CMOS circuit on a substrate comprising the steps of: sensing a power supply transition; clamping the substrate to a known potential in response to said sensing; and releasing said clamping after said transition.

Claim 9

Dependent Claim 22 words

The method of claim 6 further including biasing the substrate after said transition to provide a second control over the substrate potential.

Claim 10

Dependent Claim 14 words

The method of claim 7 further including biasing the substrate after said releasing step.

Claim 11

Dependent Claim 45 words

Apparatus for controlling latch-up in a CMOS circuit on a substrate comprising the combination of: a bias circuit coupled to control the potential of the substrate on which the CMOS circuit is located; and a control circuit for selectively enabling and disabling said bias circuit.

Claim 12

Dependent Claim 45 words

Apparatus for controlling latch-up in a CMOS circuit on a substrate comprising the combination of: a bias circuit coupled to control the potential of the substrate on which the CMOS circuit is located; and a control circuit for selectively enabling and disabling said bias circuit.

Claim 13

Dependent Claim 43 words

The apparatus according to claim 10 including: a circuit for sensing a power supply transition; a clamp circuit for clamping the substrate to a known potential in response to said sensing circuit and arranged to release said clamp after said power supply transition.

Claim 14

Dependent Claim 75 words

The circuit according to claim 10 wherein said bias circuit includes a substrate bias voltage generator coupled to the CMOS substrate, and wherein the combination further includes a circuit for detecting when the substrate potential reaches a predetermined point, said clamp circuit being responsively coupled to said detecting circuit for inhibiting said clamping in response to said detection, said circuit including means for providing substrate to ground capacitance substantially greater than the normal parasitic capacitance.

Claim 15

Dependent Claim 74 words

The circuit according to claim 9 wherein said circuit combination comprises: a circuit for sensing a power supply transition; a clamping circuit for coupling the substrate to ground in response to said sensing circuit sensing a power supply transition; and being arranged to release said clamping in response to the substantial termination of a power supply transition; and a charge pump coupled to said substrate and to said clamping circuit for biasing the substrate.

Claim 16

Dependent Claim 33 words

The apparatus according to claim 12 further including: a circuit for detecting when the substrate reaches a predetermined potential; said clamping circuit being responsively coupled to said detecting circuit for inhibiting said clamping.

Claim 17

Dependent Claim 56 words

A circuit for controlling latch-up in a CMOS circuit on a substrate comprising the combination of: a sensing circuit for sensing a power supply transition; a circuit responsively coupled to said sensing circuit for clamping the substrate to a known potential; and said control circuit being coupled to release said control after said power supply transition.

Claim 18

Dependent Claim 56 words

A circuit for controlling latch-up in a CMOS circuit on a substrate comprising the combination of: a sensing circuit for sensing a power supply transition; a circuit responsively coupled to said sensing circuit for clamping the substrate to a known potential; and said control circuit being coupled to release said control after said power supply transition.

Claim 19

Dependent Claim 27 words

The circuit combination according to claim 14 further including a substrate bias generator coupled to bias the substrate, said bias generator being coupled to said control circuit.

Claim 20

Dependent Claim 41 words

The circuit combination according to claim 15 wherein said bias generator is coupled to be permitted to bias the substrate in response to said control circuit releasing the substrate from the known potential in response to sensing a power supply transition.

Claim 21

Dependent Claim 118 words

A circuit for controlling latch-up in a CMOS circuit on a substrate comprising the combination of: means for providing a substrate to ground capacitance; a substrate bias generator coupled to the substrate for generating a bias thereon; means coupled to receive a power supply signal and for sensing a power supply transition; a clamping circuit responsively coupled to said sensing circuit for clamping the bias generator to ground potential in response to the sensing of a power supply transition; said sensing circuit being coupled to release said clamping circuit in response to sensing that the power supply transition has substantially ended, whereby the substrate bias generator biases the substrate after the power supply transition thereby to inhibit latch-up.

Claim 22

Dependent Claim 118 words

A circuit for controlling latch-up in a CMOS circuit on a substrate comprising the combination of: means for providing a substrate to ground capacitance; a substrate bias generator coupled to the substrate for generating a bias thereon; means coupled to receive a power supply signal and for sensing a power supply transition; a clamping circuit responsively coupled to said sensing circuit for clamping the bias generator to ground potential in response to the sensing of a power supply transition; said sensing circuit being coupled to release said clamping circuit in response to sensing that the power supply transition has substantially ended, whereby the substrate bias generator biases the substrate after the power supply transition thereby to inhibit latch-up.

Claim 23

Dependent Claim 39 words

The circuit combination according to claim 17 further including an inhibiting circuit responsively coupled to the substrate for detecting a predetermined potential, said circuit being controllingly coupled for inhibiting said clamping circuit in response to detecting said predetermined potential.

Claim 24

Dependent Claim 68 words

The circuit combination according to claim 17 wherein said combination includes: a clamping transistor having its source-drain path coupling the substrate bias generator to ground; a control transistor having its source-drain path coupled to connect a power supply voltage to the gate of said clamping transistor; means coupled to the gate of said control transistor for turning on said control transistor in response to a power supply transition.

Claim 25

Dependent Claim 54 words

The circuit combination according to claim 19 further including an inhibiting circuit comprising a circuit for detecting a predetermined potential on the substrate, said inhibiting circuit being controllingly coupled to the gate of said controlled transistor for preventing said control transistor from coupling the power supply source to the gate of said clamping transistor.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1989-02-17	1989-08-19	1990-02-18	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1993-02-17	1993-08-19	1994-02-18	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1997-02-17	1997-08-19	1998-02-18	$7700.00	Window Closed / Lapsed

Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits

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