Patent EP0111157A2 successfully refreshed from Google Patents.
Patent US4570259A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4570259A Expired / Lapsed US ⏱️ 0.0 years remaining

Data transmission on equipment including a plurality of data stations connected by a common transmission line

Assignee: Mitsubishi Electric Corp
•
Filing: 1982-07-07
•
Granted: 1986-02-11
•
Expires: 2002-07-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Data transmission equipment includes a plurality of data stations connected in series through a loop transmission path. A synchronizing station is connected to the data stations in the loop transmission line. The synchronizing station generates transmission signals made up of a synchronizing slot, an address slot and data transmission slots. A display board for setting and displaying data is connected to at least one of the data stations. Process line controllers are connected to data stations to transmit data related to process control to, or receive data from, a process control apparatus. The data transmission equipment further includes sensor bases connected to data stations. Each data station includes a coupling unit connected in series with the loop transmission line, transmitting and receiving units connected to the coupling unit through a bus, input units provided between the transmitting units and the sensor bases, and a bus provided between the transmitting units and the sensor bases. One embodiment of the equipment includes a buffer memory and an output buffer memory which holds the contents of the buffer memory until they are stored in an output memory.

Inventors

  • 👤 Tetsuo Ishii

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 12:58
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/423

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 189 words
A data transmission equipment comprising: a plurality of data stations connected in series through a loop transmission path; a display board connected to at least one of said data stations to set and display the data; a process line controller connected to one of said data stations; a synchronizing station connected between said data station that is connected to said display board and said data station that is connected to said process line controller; a sensor base connected between another of said data stations and process control apparatus; each of said data stations including a buffer memory having addresses for storing input/output signals, said signals being transmitted via said transmission line and said buffer memory; said data transmission equipment further comprising a multiplexer and a demultiplexer, an address counter which cyclically scans the addresses of said multiplexer and of said demultiplexer, an address selector for switching the addresses in said buffer memory, a data selector for switching the input data of said buffer memory, an output memory and an output buffer memory for holding the contents of said buffer memory until said contents are stored in said output memory.
Claim 2
Dependent Claim 189 words
A data transmission equipment comprising: a plurality of data stations connected in series through a loop transmission path; a display board connected to at least one of said data stations to set and display the data; a process line controller connected to one of said data stations; a synchronizing station connected between said data station that is connected to said display board and said data station that is connected to said process line controller; a sensor base connected between another of said data stations and process control apparatus; each of said data stations including a buffer memory having addresses for storing input/output signals, said signals being transmitted via said transmission line and said buffer memory; said data transmission equipment further comprising a multiplexer and a demultiplexer, an address counter which cyclically scans the addresses of said multiplexer and of said demultiplexer, an address selector for switching the addresses in said buffer memory, a data selector for switching the input data of said buffer memory, an output memory and an output buffer memory for holding the contents of said buffer memory until said contents are stored in said output memory.

References Cited (Backward Citations)

US3764981A Cited
US4002842A Cited
US3940561A Cited
US4335426A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-02-10 1989-08-12 1990-02-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-02-10 1993-08-12 1994-02-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-02-10 1997-08-12 1998-02-11 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag