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US4568957A
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GaAs Complementary enhancement mode junction field effect transistor structures and method of fabrication
Assignee: DRS Sensors and Targeting Systems Inc
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Filing: 1984-01-16
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Granted: 1986-02-04
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Expires: 2004-01-16
Abstract
Abstract Ultra low-power GaAs complementary junction field effect transistors are implemented in the design of complementary integrated circuits using a planar technology in conjunction with multiple and selective ion implantation. Both junction FETs, namely the p and n channel devices, are enhancement mode devices and biased in the forward direction thus leading to the advantageous DCFL (directly coupled field effect transistor logic) with one power supply, low power dissipation and high packing densities, all prerequisites for VLSI (very large scale integration).
Inventors
- 👤 Rainer Zuleeg
- 👤 Johannes K. Notthoff
- 👤 Gary L. Troeger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D84/00; H10D84/01; H10D84/0123; H10D84/02; H10D84/05
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
254 words
A GaAs integrated circuit structure containing complementary enhancement junction field effect transistors (JFET) comprising: a semi-insulating GaAs substrate having a first main surface; at least one n channel JFET structure formed in said first main surface of the substrate, the n channel structure comprising: source and drain regions formed by a first ion implantation of n type impurity ions into two regions of the substrate separated by an intermediate region; a channel region formed by exposing a portion of the intermediate region to a second ion implantation of further n type impurity ions, the second implantation also implanting into the source and drain regions; and a gate region formed by exposing a portion of the channel region to a third ion implantation of p type impurity ions; said source, drain and gate regions having electrical contacts emplaced atop them; and at least one p channel JFET structure formed in said first main surface of the substrate, the p channel structure comprising: a p channel region formed by a channel ion implantation of p type impurity ions into the substrate; source and drain regions formed by ion implantation of p type impurity ions into respective spaced-apart areas of the p channel region, the remainder of the p channel region being protected from this ion implantation; and a gate region formed by exposing a portion of the channel region intermediate the source and drain regions to an ion implantation of n type impurity ions; said source, drain and gate regions having electrical contacts emplaced atop them.
Claim 2
Dependent Claim
254 words
A GaAs integrated circuit structure containing complementary enhancement junction field effect transistors (JFET) comprising: a semi-insulating GaAs substrate having a first main surface; at least one n channel JFET structure formed in said first main surface of the substrate, the n channel structure comprising: source and drain regions formed by a first ion implantation of n type impurity ions into two regions of the substrate separated by an intermediate region; a channel region formed by exposing a portion of the intermediate region to a second ion implantation of further n type impurity ions, the second implantation also implanting into the source and drain regions; and a gate region formed by exposing a portion of the channel region to a third ion implantation of p type impurity ions; said source, drain and gate regions having electrical contacts emplaced atop them; and at least one p channel JFET structure formed in said first main surface of the substrate, the p channel structure comprising: a p channel region formed by a channel ion implantation of p type impurity ions into the substrate; source and drain regions formed by ion implantation of p type impurity ions into respective spaced-apart areas of the p channel region, the remainder of the p channel region being protected from this ion implantation; and a gate region formed by exposing a portion of the channel region intermediate the source and drain regions to an ion implantation of n type impurity ions; said source, drain and gate regions having electrical contacts emplaced atop them.
Claim 3
Dependent Claim
38 words
The structure of claim 1 wherein the ion implantations into the substrate pass through a protective layer of silicon nitride having a thickness of about 1000 angstroms, said protective layer being removed beneath at least the electrical contacts.
Claim 4
Dependent Claim
130 words
The structure of claim 1 further including an n channel resistive element which comprises: first and second contact regions formed by a first ion implantation of n type impurity ions into said regions which are separated by an interposed region, said first ion implantation being substantially similar to the first ion implantation for the n channel JFET in implant energy and ion dosage amount; and a resistive channel region formed by a second ion implantation of n type impurity ions into a portion of the interposed region, said portion connecting the contact regions, wherein the ion dosage of this implantation is less than that of the second ion implantation of the n channel JFET and at an effective level to achieve a desired level of resistance for the resistive element.
Claim 5
Dependent Claim
131 words
The structure of claim 1 further including a p channel resistive element which comprises: first and second contact regions formed by a first ion implantation of p type impurity ions into said regions which are separated by an intervening region, said first ion implantation being substantially similar in implant energy and ion dosage to the source and drain ion implantation for the p channel JFET; and a resistive channel region formed by a second ion implantation of p type impurity ions into a portion of the intervening region, said portion connecting the contact regions, wherein the ion dosage of this implantation is less than that of the channel ion implantation for the p channel JFET and at a level sufficient to achieve a desired level of resistance for the resistive element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-03 | 1989-08-05 | 1990-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-03 | 1993-08-05 | 1994-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-03 | 1997-08-05 | 1998-02-04 | $7700.00 | Window Closed / Lapsed |