Semi-conductor inverter using complementary junction field effect transistor pair

Claim 1

A complementary semiconductor integrated inverter circuit, comprising: a semiconductor substrate of one conductivity type having a high impurity concentration; an epitaxial semiconductor layer of the same conductivity type as said substrate formed on said substrate and having a low impurity concentration; a first semiconductor region of the same conductivity type as the substrate formed in a surface portion of said epitaxial layer; a second semiconductor region of the opposite conductivity type formed in a surface portion of said epitaxial layer around said first region and having a high impurity concentration; a third semiconductor region of the same conductivity type as said second region formed in a surface portion of said epitaxial layer a short distance from said second region; a fourth semiconductor region of the same conductivity type as said substrate formed in a surface portion of said third region; said substrate, first region, the portion of said epitaxial layer under said first region, and second region forming respectively the source, drain, channel and gate regions of a vertical junction field effect transistor; the third region further consisting of one end portion, another end portion and a center portion under said fourth region; said one end portion, other end portion, center portion and fourth region forming respectively the drain, source, channel and gate regions of a lateral juntion field effect transistor; input terminal means electrically connecting the respective gate regions of said vertical and lateral junction field effect transistors for defining an input terminal effective to apply an input signal applied thereto to both of said gate regions; and output terminal means electrically connecting the respective drain regions of said vertical and lateral junction field effect transistors for defining an output terminal effective to develop thereat an output signal from both of said drain regions.