US4115740A
Expired / Lapsed
US
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Push-pull pulse amplifier having improved turn-on and turn-off times
Assignee: Sony Corp
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Filing: 1977-11-11
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Granted: 1978-09-19
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Expires: 1997-11-11
Abstract
Abstract A pulse amplifier formed of first and second field effect transistors, each exhibiting an inherent input capacitance at its gate electrode, the field effect transistors being connected in push-pull relation whereby their drain or source electrodes are connected to a common output terminal. First and second resistive circuits are connected in a pulse supply circuit to supply pulse signals to the respective gate electrodes of the field effect transistors. Each of the resistive circuits exhibits a higher resistance when a pulse is supplied therethrough to turn the respective field effect transistor ON and a lower resistance when the pulse is terminated to turn the respective field effect transistor OFF. The higher resistance of the resistive circuit cooperates with the inherent input capacitance of the respective field effect transistor to provide a higher discharge time constant to turn that field effect transistor ON and the lower resistance cooperates with the inherent input capacitance of the field effect transistor to provide a lower charge time constant to turn that field effect transistor OFF, whereby the field effect transistors are not ON concurrently. In a preferred embodiment, the field effect transistors are complementary field effect transistors so that a positive-going pulse turns one of those field effect transistors OFF while turning the other ON, and a negative-going pulse turns the one field effect transistor ON while turning the other OFF.
Inventors
- 👤 Tadao Yoshida
- 👤 Tadao Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:15
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/20; H03F3/21; H03F3/217; H03F3/2171; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
249 words
A pulse amplifier, comprising first and second field effect transistors, each having an input electrode and a pair of output electrodes and each exhibiting an inherent capacitance at its input electrode, said first and second field effect transistors being connected in push-pull relation such that one of the output electrodes of each of said field effect transistors is connected in common to an output terminal, the other output electrode of each of said field effect transistors is adapted to receive a DC energizing voltage and the input electrode of each of said field effect transistors is adapted to receive a pulse signal; means for supplying pulse signals; and first and second drive circuits connected between said pulse signal supply means and the input electrodes of said first and second field effect transistors respectively, each of said drive circuits exhibiting a higher impedance when a pulse is supplied to turn the respective field effect transistor ON and a lower impedance when a pulse is terminated to turn the respective field effect transistor OFF, said higher impedance cooperating with the inherent capacitance at the input electrode of said respective field effect transistor to provide a higher discharge time constant to turn said field effect transistor ON and said lower impedance cooperating with the inherent capacitance at the input electrode of said respective field effect transistor to provide a lower charge time constant to turn said field effect transistor OFF, whereby said first and second field effect transistors are not ON concurrently.
Claim 2
Dependent Claim
249 words
A pulse amplifier, comprising first and second field effect transistors, each having an input electrode and a pair of output electrodes and each exhibiting an inherent capacitance at its input electrode, said first and second field effect transistors being connected in push-pull relation such that one of the output electrodes of each of said field effect transistors is connected in common to an output terminal, the other output electrode of each of said field effect transistors is adapted to receive a DC energizing voltage and the input electrode of each of said field effect transistors is adapted to receive a pulse signal; means for supplying pulse signals; and first and second drive circuits connected between said pulse signal supply means and the input electrodes of said first and second field effect transistors respectively, each of said drive circuits exhibiting a higher impedance when a pulse is supplied to turn the respective field effect transistor ON and a lower impedance when a pulse is terminated to turn the respective field effect transistor OFF, said higher impedance cooperating with the inherent capacitance at the input electrode of said respective field effect transistor to provide a higher discharge time constant to turn said field effect transistor ON and said lower impedance cooperating with the inherent capacitance at the input electrode of said respective field effect transistor to provide a lower charge time constant to turn said field effect transistor OFF, whereby said first and second field effect transistors are not ON concurrently.
Claim 3
Dependent Claim
39 words
The pulse amplifier of claim 1 wherein each of said drive circuits is comprised of a resistance and switch means selectively operative in response to the pulse signal supplied by said pulse signal supply means to decrease said resistance.
Claim 4
Dependent Claim
40 words
The pulse amplifier of claim 2 wherein each of said switch means comprises a diode, each said resistance includes at least two resistors connected in series, and said diode is connected in parallel with at least one of said resistors.
Claim 5
Dependent Claim
64 words
The pulse amplifier of claim 1 wherein each of said drive circuits is comprised of two resistances of different resistance values and switch means selectively operative in response to the pulse signal supplied by said pulse signal supply means to couple one or the other of said resistances between said pulse signal supply means and the input electrode of said respective field effect transistor.
Claim 6
Dependent Claim
104 words
The pulse amplifier of claim 4 wherein each of said switch means comprises two transistors, one of which being responsive to a pulse signal of predetermined polarity to couple the resistance of higher resistance value between said pulse signal supply means and said input electrode of said respective field effect transistor to turn said field effect transistor ON and the other of said transistors being responsive to the termination of said pulse signal to couple the resistance of lower resistance value between said pulse signal supply means and said input electrode of said respective field effect transistor to turn said field effect transistor OFF.
Claim 7
Dependent Claim
29 words
The pulse amplifier of claim 5 wherein said two transistors care complementary transistors, each being connected between said pulse signal supply means and a respective resistor in emitter-follower configuration.
Claim 8
Dependent Claim
50 words
The pulse amplifier of claim 1 wherein said field effect transistors are complementary field effect transistors having their drain electrodes connected in common to said output terminal, their source electrodes adapted to receive different DC energizing voltages and their gate electrodes connected to said first and second drive circuits, respectively.
Claim 9
Dependent Claim
18 words
The pulse amplifier of claim 7 wherein said complementary field effect transistors are vertical channel field effect transistors.
Claim 10
Dependent Claim
69 words
The pulse amplifier of claim 7 wherein said pulse supply means supplies rectangular pulse-wave signals to said complementary field effect transistors to turn one of said field effect transistors OFF and the other of said field effect transistors ON in response to a positive-going pulse signal and to turn said one field effect transistor ON and said other field effect transistor OFF in response to a negative-going pulse signal.
References Cited (Backward Citations)
US4028633A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-09-18 | 1982-03-20 | 1982-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-09-18 | 1986-03-20 | 1986-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-09-18 | 1990-03-20 | 1990-09-19 | $7700.00 | Window Closed / Lapsed |