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US4567593A
Expired / Lapsed
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Apparatus for verification of a signal transfer in a preselected path in a data processing system
Assignee: Bull HN Information Systems Inc
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Filing: 1983-10-06
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Granted: 1986-01-28
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Expires: 2003-10-06
Abstract
Abstract A specialized circuit set is included in a data processing system wherein the circuit set registers can be configured into a serial array. A clock signal distribution system delivers controlled clock signals to selected serial arrays. A maintenance data processor provides predetermined signal groups and addressing apparatus responsive to the predetermined signal groups loads and unloads register arrays in response to the predetermined signals. A predetermined signal group is entered into the serial register array, a predetermined number of clock cycles are applied, and the resulting signals shifted from the serial register array are applied to the maintenance data processor for display or analysis. By comparing the expected result for a given initial state with the actual result of an operation sequence, the accuracy of the operation of the data processing system, or any portion thereof, is thereby determined.
Inventors
- 👤 Lawrence D. Bashaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:42
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G06; G06F; G06F11/00; G06F11/22; G06F11/2294
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
333 words
Apparatus for verifying the operation of a data processing system, comprising: (a) maintenance means, having a maintenance processor and a maintenance memory, for controlling the execution of a test operation of the data processing system; (b) coupling means for coupling the maintenance processor to the data processing system; (c) test control means, operatively connected to said coupling means, for controlling the distribution of an input test signal, the distribution of a plurality of control signals, and the distribution of a clock signal to said data processing system; and (d) register means, operatively connected to said test control means, said register means being associated with the data processing system, said register means including: (i) at least one register of a master/slave type having at least one register position, the register having data select logic before a master latch associated with said register which can select normal input, configure the register as a shifting register, or reset the register in response to one of said control signals; or (ii) at least one register file having a plurality of registers of at least one register position, and further having a master latch, a slave register, and a data selector for each of the plurality of registers, the data selector selecting a normal input mode, a shifting mode, or a reset mode in response to one of said control signals; preselected register means being placed in the shifting mode in response to one of said control signals, the input test signal being shifted through the preselected register means in response to a shift control signal, the input test signal being analyzed by the maintenance processor after the input test signal has been shifted through the preselected register means to determine if the input test signal has an expected result, the shifting configuration of said register means providing for inversion between each register position wherein each bit of the input test signal is inverted as it is shifted, thereby permitting the analysis to identify a shift path failure.
Claim 2
Dependent Claim
333 words
Apparatus for verifying the operation of a data processing system, comprising: (a) maintenance means, having a maintenance processor and a maintenance memory, for controlling the execution of a test operation of the data processing system; (b) coupling means for coupling the maintenance processor to the data processing system; (c) test control means, operatively connected to said coupling means, for controlling the distribution of an input test signal, the distribution of a plurality of control signals, and the distribution of a clock signal to said data processing system; and (d) register means, operatively connected to said test control means, said register means being associated with the data processing system, said register means including: (i) at least one register of a master/slave type having at least one register position, the register having data select logic before a master latch associated with said register which can select normal input, configure the register as a shifting register, or reset the register in response to one of said control signals; or (ii) at least one register file having a plurality of registers of at least one register position, and further having a master latch, a slave register, and a data selector for each of the plurality of registers, the data selector selecting a normal input mode, a shifting mode, or a reset mode in response to one of said control signals; preselected register means being placed in the shifting mode in response to one of said control signals, the input test signal being shifted through the preselected register means in response to a shift control signal, the input test signal being analyzed by the maintenance processor after the input test signal has been shifted through the preselected register means to determine if the input test signal has an expected result, the shifting configuration of said register means providing for inversion between each register position wherein each bit of the input test signal is inverted as it is shifted, thereby permitting the analysis to identify a shift path failure.
Claim 3
Dependent Claim
22 words
An apparatus according to claim 1 wherein the registers of said register means include D registers, J-K registers, and multiple generator registers.
Claim 4
Dependent Claim
48 words
An apparatus according to claim 1 wherein the register files of said register means include a plurality of m×n register files, where m is the number of bit positions of a register within the register file, and where n is the number of registers within the register file.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-27 | 1989-07-29 | 1990-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-27 | 1993-07-29 | 1994-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-27 | 1997-07-29 | 1998-01-28 | $7700.00 | Window Closed / Lapsed |