Method and apparatus for the stepwise static testing of the respective connections and integrated subsystems of a microprocessor-based system for use by the general public

Claim 1

A method for testing a microprocessor-based system in case of a malfunction in said system, said system having a data bus with a first plurality of bit lines in parallel, an address bus with a second plurality of bit lines in parallel, and a third plurality of control bit lines for interconnecting said microprocessor with respective peripheral circuits (ROM, RAM) thereof, said method comprising the steps of: (a) verifying whether a significant general power supply level for said system is present; (b) verifying the presence of a correct clock signal for said system as provided by a clock signal procurement means; (c) replacing the system microprocessor by another, non-defective, microprocessor of the same type to determine whether the original system microprocessor is defective; and in case of a sufficient general supply level and a correct clock signal and the presence of said non-defective microprocessor, said system is still malfunctioning, the following steps are executed: (d) removing the non-defective microprocessor while steering all said peripheral circuits to their high-impedance output states with respect to respective ones of said first, second, and third pluralities of bit lines connected to said peripheral circuits; (e) feeding said first, second and third pluralities of bit lines with a sequence of quasi-static signal patterns for implementing the following steps for testing a predetermined peripheral circuit interconnection; (f) applying a sequence of binary signals to each bit line associated to said peripheral circuit and verifying the presence of said binary signal on the corresponding package input of said peripheral circuit; (g) verifying of the absence of short circuits between the various bit lines and/or between a line and the power supply by applying a binary signal of high level via a single bus line and a binary signal of low level via all other bus lines, and verifying that said binary signal of high level does not arrive on a bus line other than the line on which it has been dispatched, followed by the successive application of said binary high signal via all other bus lines in order to perform the same verification as before by simple permutation of signal values; (h) verifying of the absence of short circuits between the various bus lines and/or between a line and ground by dispatching a binary signal of low level (connected to ground) via a single bus line and a binary signal of high level via all other bus lines, and verifying that said other than the line on which it has been dispatched, followed by the successive application of said binary signal of low level on all other bus lines in order to perform the same verification as before by simple permutation of signal values.

Claim 2

A method for testing a microprocessor-based system in case of a malfunction in said system, said system having a data bus with a first plurality of bit lines in parallel, an address bus with a second plurality of bit lines in parallel, and a third plurality of control bit lines for interconnecting said microprocessor with respective peripheral circuits (ROM, RAM) thereof, said method comprising the steps of: (a) verifying whether a significant general power supply level for said system is present; (b) verifying the presence of a correct clock signal for said system as provided by a clock signal procurement means; (c) replacing the system microprocessor by another, non-defective, microprocessor of the same type to determine whether the original system microprocessor is defective; and in case of a sufficient general supply level and a correct clock signal and the presence of said non-defective microprocessor, said system is still malfunctioning, the following steps are executed: (d) removing the non-defective microprocessor while steering all said peripheral circuits to their high-impedance output states with respect to respective ones of said first, second, and third pluralities of bit lines connected to said peripheral circuits; (e) feeding said first, second and third pluralities of bit lines with a sequence of quasi-static signal patterns for implementing the following steps for testing a predetermined peripheral circuit interconnection; (f) applying a sequence of binary signals to each bit line associated to said peripheral circuit and verifying the presence of said binary signal on the corresponding package input of said peripheral circuit; (g) verifying of the absence of short circuits between the various bit lines and/or between a line and the power supply by applying a binary signal of high level via a single bus line and a binary signal of low level via all other bus lines, and verifying that said binary signal of high level does not arrive on a bus line other than the line on which it has been dispatched, followed by the successive application of said binary high signal via all other bus lines in order to perform the same verification as before by simple permutation of signal values; (h) verifying of the absence of short circuits between the various bus lines and/or between a line and ground by dispatching a binary signal of low level (connected to ground) via a single bus line and a binary signal of high level via all other bus lines, and verifying that said other than the line on which it has been dispatched, followed by the successive application of said binary signal of low level on all other bus lines in order to perform the same verification as before by simple permutation of signal values.

Claim 5

A device for the static testing of the connections of the peripheral integrated circuits to a microprocessor (μP) in a microprocessor-based system, said system having a data bus (BUSMUX) with a first plurality of bit lines in parallel, an address bus (ADBUS) with a second plurality of bit lines in parallel, and a third plurality of control lines (ALE, RD, WR) for interconnecting said microprocessor with respective peripheral circuits thereof, characterized in that said device comprises: attachment means (CDS) for attaching said device to the system in lieu of the microprocessor; validation means for manually validating (setting to a low impedance a first peripheral circuit while setting to a high impedance output state any other peripheral circuit; pad connection means (CDR), for connecting said device, during the validation of said first peripheral integrated circuit, to the pads of said peripheral integrated circuit, generating means for statically generating binary signals to emulate the microprocessor on said first, second and third pluralities of bit lines; first displaying means (LEDBUS) for statically displaying said binary signals as generated on at least a multiple-element subset of said first, second and third pluralities of bit lines; second displaying means (LEDCPD) for the static display of the binary signals effectively appearing on the pads of said first peripheral integrated circuit; third displaying means (LEDVALD) for the static display of the binary signals originating from outputs of said first peripheral integrated circuit and received by the device in lieu of the microprocessor.

Claim 6

A device for the static testing of the connections of the peripheral integrated circuits to a microprocessor (μP) in a microprocessor-based system, said system having a data bus (BUSMUX) with a first plurality of bit lines in parallel, an address bus (ADBUS) with a second plurality of bit lines in parallel, and a third plurality of control lines (ALE, RD, WR) for interconnecting said microprocessor with respective peripheral circuits thereof, characterized in that said device comprises: attachment means (CDS) for attaching said device to the system in lieu of the microprocessor; validation means for manually validating (setting to a low impedance a first peripheral circuit while setting to a high impedance output state any other peripheral circuit; pad connection means (CDR), for connecting said device, during the validation of said first peripheral integrated circuit, to the pads of said peripheral integrated circuit, generating means for statically generating binary signals to emulate the microprocessor on said first, second and third pluralities of bit lines; first displaying means (LEDBUS) for statically displaying said binary signals as generated on at least a multiple-element subset of said first, second and third pluralities of bit lines; second displaying means (LEDCPD) for the static display of the binary signals effectively appearing on the pads of said first peripheral integrated circuit; third displaying means (LEDVALD) for the static display of the binary signals originating from outputs of said first peripheral integrated circuit and received by the device in lieu of the microprocessor.