Patent US4566940A successfully refreshed from Google Patents.
US4566940A
Expired / Lapsed
US
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Manufacturing process for semiconductor integrated circuits
Assignee: NTT Inc
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Filing: 1984-10-17
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Granted: 1986-01-28
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Expires: 2004-10-17
Abstract
Abstract A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.
Inventors
- 👤 Manabu Itsumi
- 👤 Kohei Ehara
- 👤 Susumu Muramoto
- 👤 Seitaro Matsuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:40
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/058; H10P; H10P76/00; H10P76/20; H10P76/202; H10W10/00; H10W10/01; H10W10/011; H10W10/10; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/951
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
109 words
A method for the manufacture of a semiconductor integrated circuit, comprising the step of: forming a resist pattern on a first material layer of a semiconductor substrate; removing a portion of said first material layer through using said resist pattern as a mask to form a recess in said first material layer; forming a second material layer by a plasma deposition process to thickness substantially equal to the depth of said recess so as to fill said recess; and removing said second material layer on said resist pattern by a lift-off process, along with said resist pattern; wherein said steps are each carried out repeatedly at least four times.
Claim 2
Independent Claim
109 words
A method for the manufacture of a semiconductor integrated circuit, comprising the step of: forming a resist pattern on a first material layer of a semiconductor substrate; removing a portion of said first material layer through using said resist pattern as a mask to form a recess in said first material layer; forming a second material layer by a plasma deposition process to thickness substantially equal to the depth of said recess so as to fill said recess; and removing said second material layer on said resist pattern by a lift-off process, along with said resist pattern; wherein said steps are each carried out repeatedly at least four times.
Claim 3
Independent Claim
402 words
A method for the manufacture on a semiconductor integrated circuit, comprising the steps of: forming a first resist pattern on a semiconductor substrate; removing a portion of said semiconductor substrate through using said first resist pattern as a mask to form a groove in said semiconductor substrate; filling up said groove with an insulating material by a plasma deposition process; removing said insulating material on said first resist pattern by a lift-off process, together with said first resist pattern; forming an insulating film on said semiconductor substrate; forming on said insulating film a first conductor layer which will ultimately serve as a gate electrode; forming a second resist pattern on said first conductor layer; removing a portion of said first conductor layer through using said second resist pattern as a mask to form a recess in said first conductor layer; forming a source region and a drain region in said semiconductor substrate through using said first conductor layer as a mask; filling up said recess of said first conductor layer with a first insulating layer by the plasma deposition process; removing said insulating layer on said second resist pattern by the lift-off process, together with said second resist pattern; forming a third resist pattern on said first conductor layer and said insulating layer; removing said insulating film and said first insulating layer on said source and drain regions through using said third resist pattern as a mask to form recesses in said insulating film and said first insulating layer; filling said recesses of said insulating film and said first insulating layer, by the plasma deposition process, with another first conductor layer which is different from said first conductor layer and will form a source electrode and a drain electrode; removing said another first conductor layer on said third resist pattern by the lift-off process, together with said third resist pattern; forming a second conductor layer on said another first conductor layer and said first insulating layer; forming a fourth resist pattern on said second conductor layer; removing a portion of said second conductor layer through using said fourth resist pattern as a mask to form a recess in said second conductor layer; filling up said recess of said second conductor layer with a second insulating layer by the plasma deposition process; and removing said second insulating layer on said fourth resist pattern by the lift-off process, together with said fourth resist pattern.
Claim 4
Independent Claim
402 words
A method for the manufacture on a semiconductor integrated circuit, comprising the steps of: forming a first resist pattern on a semiconductor substrate; removing a portion of said semiconductor substrate through using said first resist pattern as a mask to form a groove in said semiconductor substrate; filling up said groove with an insulating material by a plasma deposition process; removing said insulating material on said first resist pattern by a lift-off process, together with said first resist pattern; forming an insulating film on said semiconductor substrate; forming on said insulating film a first conductor layer which will ultimately serve as a gate electrode; forming a second resist pattern on said first conductor layer; removing a portion of said first conductor layer through using said second resist pattern as a mask to form a recess in said first conductor layer; forming a source region and a drain region in said semiconductor substrate through using said first conductor layer as a mask; filling up said recess of said first conductor layer with a first insulating layer by the plasma deposition process; removing said insulating layer on said second resist pattern by the lift-off process, together with said second resist pattern; forming a third resist pattern on said first conductor layer and said insulating layer; removing said insulating film and said first insulating layer on said source and drain regions through using said third resist pattern as a mask to form recesses in said insulating film and said first insulating layer; filling said recesses of said insulating film and said first insulating layer, by the plasma deposition process, with another first conductor layer which is different from said first conductor layer and will form a source electrode and a drain electrode; removing said another first conductor layer on said third resist pattern by the lift-off process, together with said third resist pattern; forming a second conductor layer on said another first conductor layer and said first insulating layer; forming a fourth resist pattern on said second conductor layer; removing a portion of said second conductor layer through using said fourth resist pattern as a mask to form a recess in said second conductor layer; filling up said recess of said second conductor layer with a second insulating layer by the plasma deposition process; and removing said second insulating layer on said fourth resist pattern by the lift-off process, together with said fourth resist pattern.
Claim 5
Dependent Claim
25 words
A method for the manufacture of a semiconductor integrated circuit according to claim 2 wherein said plasma deposition process is an ECR plasma deposition process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-27 | 1989-07-29 | 1990-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-27 | 1993-07-29 | 1994-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-27 | 1997-07-29 | 1998-01-28 | $7700.00 | Window Closed / Lapsed |