Semiconductor device and method for manufacturing the same

Claim 1

A method for manufacturing a bipolar semiconductor device comprising vertical npn and pnp transistors, comprising the steps of: (a) forming at least a pair of grooves having different depths in a surface of a semiconductor substrate of a first conductivity type; (b) diffusing a high concentration of impurity of a second conductivity type in a surface including said at least a pair of grooves; (c) forming an epitaxial layer of the second conductivity type on said surface including said at least a pair of grooves such that said epitaxial layer has a thickness greater than a depth of a shallow groove of said at least a pair of grooves and such that an upper surface of said epitaxial layer in a deep groove of said at least a pair of grooves is substantially lower than said surface of said semiconductor substrate; (d) diffusing a high concentration of impurity of the first conductivity type in said upper surface of said epitaxial layer of the second conductivity type after a mask layer is formed on a portion of said epitaxial layer which corresponds to said shallow groove; (e) forming an epitaxial layer of the first conductivity type on said surface including said at least a pair of grooves; (f) etching an entire surface to be level, to expose said surface of said semiconductor substrate, thereby to leave epitaxial layers of the first and second conductivity types in said at least a pair of grooves, respectively, said epitaxial layers of the first and second conductivity types having the same depth and width; (g) forming a base region and an emitter in said epitaxial layers in said at least a pair of grooves, respectively, thereby to form the npn and pnp transistors; and (h) forming base and emitter electrodes, each connected respectively to the base and emitter regions, and collector electrodes connected respectively to the impurity diffusion layers formed in the step (c) and the step (d).

Claim 2

A method for manufacturing a bipolar semiconductor device comprising vertical npn and pnp transistors, comprising the steps of: (a) forming at least a pair of grooves having different depths in a surface of a semiconductor substrate of a first conductivity type; (b) diffusing a high concentration of impurity of a second conductivity type in a surface including said at least a pair of grooves; (c) forming an epitaxial layer of the second conductivity type on said surface including said at least a pair of grooves such that said epitaxial layer has a thickness greater than a depth of a shallow groove of said at least a pair of grooves and such that an upper surface of said epitaxial layer in a deep groove of said at least a pair of grooves is substantially lower than said surface of said semiconductor substrate; (d) diffusing a high concentration of impurity of the first conductivity type in said upper surface of said epitaxial layer of the second conductivity type after a mask layer is formed on a portion of said epitaxial layer which corresponds to said shallow groove; (e) forming an epitaxial layer of the first conductivity type on said surface including said at least a pair of grooves; (f) etching an entire surface to be level, to expose said surface of said semiconductor substrate, thereby to leave epitaxial layers of the first and second conductivity types in said at least a pair of grooves, respectively, said epitaxial layers of the first and second conductivity types having the same depth and width; (g) forming a base region and an emitter in said epitaxial layers in said at least a pair of grooves, respectively, thereby to form the npn and pnp transistors; and (h) forming base and emitter electrodes, each connected respectively to the base and emitter regions, and collector electrodes connected respectively to the impurity diffusion layers formed in the step (c) and the step (d).