Patent US4566104A successfully refreshed from Google Patents.
US4566104A
Expired / Lapsed
US
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Testing digital electronic circuits
Assignee: Fujitsu Services Ltd
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Filing: 1983-10-26
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Granted: 1986-01-21
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Expires: 2003-10-26
Abstract
Abstract A large-scale integrated circuit chip includes a plurality of bistables connected to combinational logic. In a diagnostic mode, the bistables are operated as a serial shift register, allowing test data to be shifted through the chip between diagnostic input and output pins (LPIN,LPOUT). In a chip test mode, the serial shift register is split into a number of shift register portions, each of which is connected between a separate pair of input and output pins. This allows test data to be shifted through all the shift register portions in parallel so as to speed up testing of the chip.
Inventors
- 👤 George M. Bradshaw
- 👤 Peter L. L. Desyllas
- 👤 Keith McLaren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:45
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
312 words
A digital electronic circuit comprising: (a) a plurality of data storage elements having respective inputs and outputs, (b) a combinational logic network having a plurality of inputs and outputs, (c) first connection means connecting the outputs of at least some of the data storage elements to respective inputs of the combinational logic network and connecting at least some of the outputs of the combinational logic network to respective inputs of the data storage elements, (d) a plurality of input and output terminals, (e) second connection means connecting all the data storage elements together in series by way of their inputs and outputs, between a pair of said input and output terminals, thereby forming a serial shift path, (f) a control line for receiving a shift control signal, the control line being connected to all the data storage elements for enabling each of the data storage elements to receive data from said serial shift path, (g) at least one first multiplexer connected in said serial shift path and having (i) a first input connected to the output of one of said data storage circuits, (ii) a second input connected to one of the said input terminals, and (iii) an output connected to the input of another one of said data storage circuits, (h) at least one second multiplexer having (i) a first input connected to one of said outputs of the combinational logic network (ii) a second input connected to the output of one of said data storage elements, and (iii) an output connected to one of the said output terminals, and (j) a further control line for receiving a test mode control signal, the further control line being connected to all said first and second multiplexers for switching each said multiplexer to select its first input when the test mode control signal has one value and otherwise to select its second input.
Claim 2
Dependent Claim
312 words
A digital electronic circuit comprising: (a) a plurality of data storage elements having respective inputs and outputs, (b) a combinational logic network having a plurality of inputs and outputs, (c) first connection means connecting the outputs of at least some of the data storage elements to respective inputs of the combinational logic network and connecting at least some of the outputs of the combinational logic network to respective inputs of the data storage elements, (d) a plurality of input and output terminals, (e) second connection means connecting all the data storage elements together in series by way of their inputs and outputs, between a pair of said input and output terminals, thereby forming a serial shift path, (f) a control line for receiving a shift control signal, the control line being connected to all the data storage elements for enabling each of the data storage elements to receive data from said serial shift path, (g) at least one first multiplexer connected in said serial shift path and having (i) a first input connected to the output of one of said data storage circuits, (ii) a second input connected to one of the said input terminals, and (iii) an output connected to the input of another one of said data storage circuits, (h) at least one second multiplexer having (i) a first input connected to one of said outputs of the combinational logic network (ii) a second input connected to the output of one of said data storage elements, and (iii) an output connected to one of the said output terminals, and (j) a further control line for receiving a test mode control signal, the further control line being connected to all said first and second multiplexers for switching each said multiplexer to select its first input when the test mode control signal has one value and otherwise to select its second input.
Claim 3
Dependent Claim
28 words
A circuit as claimed in claim 1 wherein the second input of said first multiplexer is also connected to one of said inputs of the combinational logic network.
Claim 4
Dependent Claim
62 words
A circuit as claimed in claim 1 wherein there is a plurality of said first and second multiplexers, each first multiplexer being associated with a respective one of the second multiplexers and wherein the first input of each said first multiplexer and the second input of the associated second multiplexer are both connected to the output of the same data storage element.
Claim 5
Dependent Claim
23 words
A circuit according to claim 1 wherein the storage elements and combinational logic network are all parts of a single integrated circuit chip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-20 | 1989-07-22 | 1990-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-20 | 1993-07-22 | 1994-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-20 | 1997-07-22 | 1998-01-21 | $7700.00 | Window Closed / Lapsed |