Digital signal transmitting and receiving system for serial data which can be easily decoded

Claim 2

Apparatus for transmitting and receiving binary data in pulse-code-modulation of audio signals which are sampled at a sampling frequency higher than audio frequency and are encoded to form data words of a number of data bits and a number of control or user bits each within the time period T and including one or more word sync pulses of which at least one pulse has a time period of 0.5nT where "n" is an integer other than two comprising transmitting means for encoding and transmitting said data words, means receiving said data words from said transmitting means and comprising a word sync sampling circuit which receives said incoming data words and a high frequency clock signal input which has a frequency high enough to discriminate each time period 0.5nT and reproducing the word sync signal in data (WSD), a bit clock signal, and serial data signals, a first shift register receiving said bit clock signals and said serial data signals from said word sync sampling circuit and converting the data from serial to parallel form, a first flip-flop circuit receiving said parallel data from said first shift register and said word sync signal in data (WSD) and said bit clock signals from said word sync sampling circuit, a decoding means receiving the parallel data from said first flip-flop and receiving receiver generated clock signals and said decoding means producing output serial data words synchronized with said generator clock signals.

Claim 3

Apparatus for transmitting and receiving binary data according to claim 1 wherein said decoding means is a second shift register.

Claim 4

Apparatus for transmitting and receiving binary data according to claim 1 wherein said decoding means is a second flip-flop circuit.

Claim 5

Apparatus for receiving binary data according to claim 1 wherein said word sync sampling circuit comprises, a second flip-flop which receives said incoming data word signals, a third flip-flop which receives the output of said second flip-flop, said second and third flip-flops receiving said high frequency clock signal, a first exclusive OR gate receiving the outputs of said second and third flip-flops, a first counter receiving the output of said first exclusive OR gate, a logic matrix circuit receiving the outputs of said first counter and the output of said first exclusive OR gate, a second counter receiving the output of said logic matrix circuit, a fourth flip-flop receiving the outputs of said second counter and said third flip-flop and producing said serial data signals, an output of said second counter comprising said bit clock signals, and a fifth flip-flop receiving an output of said second counter and supplying said word sync signal (WSD) as an output.

Claim 6

Apparatus according to claim 4 including a sixth flip-flop receiving an output of said logic matrix circuit and said high frequency clock signal and supplying an output to said fifth flip-flop.

Claim 7

Apparatus according to claim 4 including an OR gate connected between said logic matrix circuit and said second counter and OR gate receiving an output of said second counter.

Claim 8

A digital signal transmission system for encoded audio signals comprising: binary data transmitter means including means for sampling audio signals, means for encoding the output of said sampling means to form data bits representing said encoded audio signals, means to form data words each of which comprises said data bits, control or user bits and a word sync signal, each of said bits having a time period T and each of said word sync signals comprising pulses of which at least one in each said word sync signal has a time period of 0.5nt where n is an integer other than two, and means to assemble said data words into blocks of said data words to identify said blocks; and receiver means for receiving said data blocks from said transmitter means and including a word sync sampling circuit which receives said incoming data words and a clock signal of frequency sufficiently high to discriminate each said pulse of time period 0.5nt, and which reproduces said word sync signals, a bit clock signal synchronized with said word sync signals, and serial data signals and wherein said word sync sampling circuit comprises a first flip-flop which receives said incoming data word signals, a second flip flop which receives the output of said first flip flop, said first and second flip flops receiving said clock signal, an exclusive OR gate receiving the outputs of said first and second flip flops, a first counter receiving the output of said exclusive OR gate, a logic matrix circuit receiving the outputs of said exclusive OR gate and said first counter, a second counter receiving the output of said logic matrix circuit, a third flip flop receiving the outputs of said second counter and said second flip flop and producing serial data signals, an output of said second counter comprising said clock signal, and a fourth flip flop receiving an output of said second counter and supplying said word sync signals as an output.

Claim 9

A digital signal transmission system for encoded audio signals comprising: binary data transmitter means including means for sampling audio signals, means for encoding the output of said sampling means to form data bits representing said encoded audio signals, means to form data words each of which comprises said data bits, control or user bits and a word sync signal, each of said bits having a time period T and each of said word sync signals comprising pulses of which at least one in each said word sync signal has a time period of 0.5nt where n is an integer other than two, and means to assemble said data words into blocks of said data words to identify said blocks; and receiver means for receiving said data blocks from said transmitter means and including a word sync sampling circuit which receives said incoming data words and a clock signal of frequency sufficiently high to discriminate each said pulse of time period 0.5nt, and which reproduces said word sync signals, a bit clock signal synchronized with said word sync signals, and serial data signals and wherein said word sync sampling circuit comprises a first flip-flop which receives said incoming data word signals, a second flip flop which receives the output of said first flip flop, said first and second flip flops receiving said clock signal, an exclusive OR gate receiving the outputs of said first and second flip flops, a first counter receiving the output of said exclusive OR gate, a logic matrix circuit receiving the outputs of said exclusive OR gate and said first counter, a second counter receiving the output of said logic matrix circuit, a third flip flop receiving the outputs of said second counter and said second flip flop and producing serial data signals, an output of said second counter comprising said clock signal, and a fourth flip flop receiving an output of said second counter and supplying said word sync signals as an output.

Claim 10

A digital signal transmission system according to claim 7 wherein said receiver means further includes means for converting said serial data signals from serial to parallel data form.

Claim 11

A digital signal transmission system according to claim 8 wherein said receiver means comprises means for receiving said parallel data and receiver generated clock signals, and for producing output serial data words synchronized with said receiver generated clock signals.

Claim 12

Apparatus for transmitting and receiving binary date in the form of data words, each of which comprises data bits representing pulse code modulated audio signals, control or user bits, and a word sync signal, each of said bits having a time period T and each of said word sync signals comprising pulses of which at least one in each said word sync signal has a time period of 0.5nt where n is an integer other than two, the apparatus comprising transmitter means for encoding and transmitting said data words, receiver means for receiving said data words from said transmitter means and comprising a word sync sampling circuit which receives said incoming data words and a clock signal of frequency sufficiently high to discriminate each said pulse of time period 0.5nt, and which reproduces said word sync signals, a bit clock signal synchronized with said word sync signals, and serial data signals, a first shift register for receiving said bit clock signals and said serial data signals from said word sync sampling circuit and converting the data from serial to parallel form, a first flip-flop circuit for receiving said parallel data from said first shift register, and said word sync signal and said bit clock signals from said word sync sampling circuit, and decoder means for receiving said parallel data from said first flip-flop circuit and receiving receiver generated clock signals, said decoder means producing output serial data words synchronized with said receiver generated clock signals.

Claim 13

Apparatus for transmitting and receiving binary date in the form of data words, each of which comprises data bits representing pulse code modulated audio signals, control or user bits, and a word sync signal, each of said bits having a time period T and each of said word sync signals comprising pulses of which at least one in each said word sync signal has a time period of 0.5nt where n is an integer other than two, the apparatus comprising transmitter means for encoding and transmitting said data words, receiver means for receiving said data words from said transmitter means and comprising a word sync sampling circuit which receives said incoming data words and a clock signal of frequency sufficiently high to discriminate each said pulse of time period 0.5nt, and which reproduces said word sync signals, a bit clock signal synchronized with said word sync signals, and serial data signals, a first shift register for receiving said bit clock signals and said serial data signals from said word sync sampling circuit and converting the data from serial to parallel form, a first flip-flop circuit for receiving said parallel data from said first shift register, and said word sync signal and said bit clock signals from said word sync sampling circuit, and decoder means for receiving said parallel data from said first flip-flop circuit and receiving receiver generated clock signals, said decoder means producing output serial data words synchronized with said receiver generated clock signals.

Claim 14

Apparatus according to claim 10 wherein said decoder means comprises a second shift register.

Claim 15

Apparatus according to claim 10 wherein said decoder means comprises a second flip-flop circuit.

Claim 16

Apparatus according to claim 10 wherein said word sync sampling circuit comprises a third flip-flop for receiving said incoming data word signals, a fourth flip-flop for receiving the output of said third flip-flop, said third and fourth flip-flops receiving said high frequency clock signal, exclusive OR circuit for receiving the outputs of said third and fourth flip-flops, a first counter for receiving the output of said exclusive OR circuit, a logic matrix circuit for receiving the outputs of said first counter and the output of said exclusive OR circuit, a second counter for receiving the output of said logic matrix circuit, a fifth flip-flop for receiving the outputs of said second counter and said fourth flip-flop and for producing said serial data signals, an output of said second counter comprising said bit clock signals, and a sixth flip-flop for receiving an output of said second counter and for supplying said word sync signal as an output.

Claim 17

Apparatus according to claim 13 comprising a seventh flip-flop for receiving an output of said logic matrix circuit and said high frequency clock signal and supplying an output to said sixth flip-flop.

Claim 18

Apparatus according to claim 13 comprising an OR circuit connected between said logic matrix circuit and said second counter, said OR circuit receiving an output of said second counter.