Method of and detecting circuit for synchronizing master-remote signalling system

Claim 2

Method of synchronizing a receiver in a digital signalling system of the master-remote type in which data is transmitted in the form of trains of electrical pulses of uniform length comprising transmitting at least two pulses each longer than the pulses used to transmit data and different in length from an integral number of the data pulses, the longer pulses being of predetermined polarities, distinguishing the longer pulses at the receiver from the pulses of uniform length, and synchronizing the receiver in response to the longer pulses.

Claim 3

Method according to claim 1 wherein the longer pulses are each one and one-half times as long as the pulses used to transmit data.

Claim 4

Method according to claim 1 wherein the first one of the longer pulses indicates a condition different from the ''''idle,'''' or ''''stand-by'''' condition of the transmitter, and the second one indicates the ''''idle'''' condition.

Claim 5

Method according to claim 1 including the step of generating a momentary signal at a predetermined time following the end of the longer pulses to indicate to the receiver the exact start of the train of pulses used to transmit data.

Claim 6

An electrical circuit for detecting a series of electrical pulses of longer length than other pulses for establishing synchronization between a transmitter and a receiver in a digital signalling system of the master-remote type, said circuit comprising a clock for producing a continuous series of clock pulses, a counter for counting clock pulses to a total exceeding the duration of the long pulses, input gate means for controlling the input to said counter, output gate means for controlling the output of said counter, a divide-by-four counter responsive to said output gate means for selectively inhibiting and partially enabling said input gate means and said output gate means, means for applying clock pulses to said input gate means, said output gate means being arranged to step said divide-by-four counter when the incoming signal changes In a predetermined direction during a predetermined interval after the start of counting corresponding to the duration of the longer pulses to be detected so that said divide-by-four counter stops only in response to the longer pulses.

Claim 7

An electrical circuit for detecting a series of electrical pulses of longer length than other pulses for establishing synchronization between a transmitter and a receiver in a digital signalling system of the master-remote type, said circuit comprising a clock for producing a continuous series of clock pulses, a counter for counting clock pulses to a total exceeding the duration of the long pulses, input gate means for controlling the input to said counter, output gate means for controlling the output of said counter, a divide-by-four counter responsive to said output gate means for selectively inhibiting and partially enabling said input gate means and said output gate means, means for applying clock pulses to said input gate means, said output gate means being arranged to step said divide-by-four counter when the incoming signal changes In a predetermined direction during a predetermined interval after the start of counting corresponding to the duration of the longer pulses to be detected so that said divide-by-four counter stops only in response to the longer pulses.

Claim 8

An electrical circuit for detecting a series of electrical pulses of longer length than other pulses for establishing synchronization between a transmitter and a receiver in a digital signalling system of the master-remote type, said circuit comprising: a. a master clock for producing a continuous series of time-spaced clock pulses shorter in duration than the pulses to be detected, b. a first counter for counting clock pulses to a total exceeding the duration of the long pulses to be detected, c. input gate means for applying pulses from the master clock of the receiver to said counter, d. output gate means responsive to said counter for producing a control signal starting and ending at predetermined counts, e. a second counter, f. means for tripping said second counter in response to a change in the incoming signal that occurs during the control signal produced by said output gate means, g. gate means connected between said second counter and said tripping means in accordance with the instantaneous conditions of said second counter, and h. means for resetting said first and second counters in response to a change in the incoming signal that occurs at a time other than during the control signal produced by said output gate means.

Claim 9

An electrical circuit for detecting a series of electrical pulses of longer length than other pulses for establishing synchronization between a transmitter and a receiver in a digital signalling system of the master-remote type, said circuit comprising: a. a master clock for producing a continuous series of time-spaced clock pulses shorter in duration than the pulses to be detected, b. a first counter for counting clock pulses to a total exceeding the duration of the long pulses to be detected, c. input gate means for applying pulses from the master clock of the receiver to said counter, d. output gate means responsive to said counter for producing a control signal starting and ending at predetermined counts, e. a second counter, f. means for tripping said second counter in response to a change in the incoming signal that occurs during the control signal produced by said output gate means, g. gate means connected between said second counter and said tripping means in accordance with the instantaneous conditions of said second counter, and h. means for resetting said first and second counters in response to a change in the incoming signal that occurs at a time other than during the control signal produced by said output gate means.