Digital signal receiver

Claim 1

A digital signal receiver for receiving a transmitted digital signal including a data signal including a bit serial type of data and a reference clock signal and a specified code signal preceding said data signal, comprising: (a) demodulating means for receiving and demodulating said digital signal being transmitted; (b) slicer means for slicing at a predetermined level the digital signal demodulated by said demodulating means; (c) sampling clock signal generating means for generating a sampling clock signal which is produced in synchronization with said reference clock signal included in an output signal from said slicer means; (d) serial/parallel converting means for sampling said output signal from said slicer means with said sampling clock signal for reproducing said data signal and said specified code signal, and converting the bit serial type of data in said data signal to a bit parallel type of data; (e) detecting means for detecting an error in at least one of the specified code or the bit parallel type of data in an output from said serial/parallel converting means, so that non-coincidence of a bit phase is detected between said sampling clock signal and the data signal included in said slicer output signal caused due to a group delay characteristics of a transmission path including a path from transmitter to said demodulating stage; (f) group delay characteristic correcting means disposed within a transmission path between said demodulating means and said slicer means for the purpose of correction of non-coincidence of said bit phase, said correcting means being responsive to the error detection output from said error detecting means for flattening the total group delay characteristic of the transmission path, including the correcting means, from a transmitter to an input terminal of said slicer means.