Frame synchronization system

Claim 2

A frame synchronization system comprising: a source of binary information signal having a given bit rate and containing a synchronization component; first means to produce a plurality of timing signals; second means coupled to said source and said first means to examine successive bits of said information signal to recognize said synchronization component and produce a resultant output signal at each examination indicating either an insynchronization condition or an out-of-synchronization condition; logic circuitry coupled to said first and second means; and a dual decision circuit coupled between said second means and said logic circuitry producing a pair of control signals to activate said logic circuitry, when said resultant output signal and both said pair of control signals indicate an outof-synchronization condition, for timing adjustment of said timing signals to achieve frame synchronization; said dual decision circuit including third means having a first, relatively long time constant and a reference operating level, fourth means having a second, relatively short time constant producing one of said pair of control signals, and fifth means coupled to said third and fourth means to produce the other of said pair of control signals and to reset said third means to said reference operating level when said other of said pair of control signals indicates an out-ofsynchronization condition.

Claim 3

A system according to claim 1, wherein said first means further produces a local binary synchronization reference signal; and said second means includes digital comparison means coupled to said source and said first means to compare the binary condition of successive bits of said information signal and the binary condition of said reference signal and produce said resultant output signal.

Claim 4

A system according to claim 1, wherein said third means includes a first integrator coupled to said second means having said first time constant and said reference operating level, a first amplitude comparator coupled to the output of said first integrator; said fourth means includes a second integrator coupled to said second means having said second time constant, a second amplitude comparator coupled to the output of said second integrator to produce said one of said pair of control signals, and a third amplitude comparator coupled to the output of said second integrator; and said fifth means includes a bistable means coupled to the output of said first and third comparators to produce said other of said pair of control signals, and a unidirectional device coupled between the output of said bistable means and the input of said first integrator to reset said first integrator to said reference operating level when said other of said pair of control signals indicates an out-of-synchronization condition.

Claim 5

A system according to claim 3, wherein said bistable means includes a flip flop having its ''''1'''' input coupled to the output of said first comparator, its ''''0'''' input coupled to the output of said third comparator and its ''''1'''' output producing said other of said pair of control signals; and said unidirectional device including a diode coupled between the ''''0'''' output of said flip flop and the input of said first integrator, said diode being poled to be reverse biased when said other of said pair of control signals indicates an in-synchronization condition and forward biased when said other of said pair of control signals indicates an out-of-synchronization condition to reset said first integrator to said reference operating level.

Claim 6

A system according to claim 1, wherein said third means include a second source of bias voltage, a first resistor coupled to said second means, a first operational amplifier having an inverting input coupled to said second source, and an Output, a first capacitor coupled between said output and said inverting input of said first amplifier, said first amplifier having said reference operating level, said first resistor and said first capacitor providing said first time constant, a third source of bias voltage, and a second operational amplifier having an inverting input coupled to said output of said first amplifier, a non-inverting input coupled to said third source, and an output; said fourth means includes a fourth source of bias voltage, a second resistor coupled to said second means, a third operational amplifier having an inverting input coupled to said second resistor, a non-inverting input coupled to said fourth source, and an output, a second capacitor coupled between said output and said inverting input of said third amplifier, said second resistor and said second capacitor providing said second time constant, a clamp circuit coupled in parallel with said second capacitor, a fifth source of bias voltage, a fourth operational amplifier having an inverting input coupled to said fifth source, a non-inverting input coupled to said output of said third amplifier, and an output, a sixth source of bias voltage, and a fifth operational amplifier having an inverting input coupled to said output of said third amplifier, a non-inverting input coupled to said sixth source, and an output providing said one of said pair of control signals; and said fifth means includes a flip flop having a ''''1'''' input coupled to said output of said second amplifier, a ''''0'''' input coupled to said output of said fourth amplifier, a ''''1'''' output to produce said other of said pair of control signals, and a ''''0'''' output, and a diode coupled between said ''''0'''' output and said inverting input of said first amplifier, said diode being poled to be reverse biased when said other of said pair of control signals is in said second condition and forward biased when said other of said pair of control signals is in said first condition to reset said first amplifier to said reference operating level.