Abstract An integrated circuit memory is provided wherein an array of memory elements is addressed by a decoder circuit responding to an address signal. The decoder circuit includes a plurality of sections, each one thereof being used to address a different section of the array. A decoder section selector is provided which, in response to the addressing signal, determines the section of the array being addressed and electrically couples the one of the plurality of decoder circuit sections which is coupled to such addressed array section to a power source while electrically decoupling the remaining section of the decoder circuit from such power source. With such arrangement, only a portion of the decoder circuit is electrically coupled to the power source when addressing the array thereby reducing the power consumption of the integrated circuit memory.
Inventors
👤 Bruce G. Armstrong
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-08 21:14
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/06; G11C8/12
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
154 words
A memory circuit comprising: (a) a matrix of memory elements; (b) a decoder circuit responsive to an address signal for selectively addressing the memory elements in the matrix, said decoder circuit having a plurality of sections for selectively addressing the meory elements in different, corresponding sections of the matrix; (c) a decoder section selector for electrically coupling one of the sections of the decoder to a power source while electrically decoupling the remaining sections of the decoder from said power source selectively in response to the address signal; and (d) wherein the decoder circuit comprises a plurality of gates each one thereof having an input transistor coupled to the address signals and to the decoder section selector and an output transistor fed by the input transistor having an output electrode coupled to the matrix of memory elements and an additional electrode adapted for coupling to the power source independent of the decoder section selector.
Claim 2
Dependent Claim
154 words
A memory circuit comprising: (a) a matrix of memory elements; (b) a decoder circuit responsive to an address signal for selectively addressing the memory elements in the matrix, said decoder circuit having a plurality of sections for selectively addressing the meory elements in different, corresponding sections of the matrix; (c) a decoder section selector for electrically coupling one of the sections of the decoder to a power source while electrically decoupling the remaining sections of the decoder from said power source selectively in response to the address signal; and (d) wherein the decoder circuit comprises a plurality of gates each one thereof having an input transistor coupled to the address signals and to the decoder section selector and an output transistor fed by the input transistor having an output electrode coupled to the matrix of memory elements and an additional electrode adapted for coupling to the power source independent of the decoder section selector.
Claim 3
Dependent Claim
20 words
The memory circuit recited in claim 1 wherein the matrix of memory elements includes a plurality of non-volatile memory elements.