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US4559626A
Expired / Lapsed
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Portable minicomputer for testing memories
Assignee: United States Department of the Air Force
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Filing: 1983-04-05
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Granted: 1985-12-17
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Expires: 2003-04-05
Abstract
Abstract A portable high speed minicomputer tester is disclosed for isolating failures in a random access memory. The device includes a central processing unit having an address counter and means for generating a plurality of test words. Individual test words are generated automatically and stored in both an internal memory and the memory under test. At a predetermined address, a test word is read out of the memories and compared. If there are any discrepancies, the minicomputer sets a latch corresponding to the failed test word bit and identifies the failed bit on a digital display readout. Using fault conversion tables, an operator can trace a discrepancy to the bit location of a memory chip in the memory under test.
Inventors
- 👤 Carleston O. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:02
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
198 words
A portable minicomputer for testing a random access memory wherein the memory comprises an array of individual memory chips each containing a multitude of address bits, said portable minicomputer comprising: a central processing unit; an internal memory connected to said central processing unit; means for connecting a memory under test to said central processing unit, said central processing unit including an address counter means for incrementing address lines of said internal memory and said memory under test, and means for generating a plurality of test words; means for writing said test words into said internal memory and said memory under test; means for reading said test words out of said internal memory and said memory under test after said address counter means reaches a predetermined address count; means for comparing said test words read out of said internal memory and said memory under test, said last mentioned means including a fault display indicating a discrepancy between test word bits; and fault conversion means comprising a table of fault display indicia and memory chip addresses for converting a discrepancy identified by said fault display into the address bit location of an individual memory chip in said memory under test.
Claim 2
Dependent Claim
198 words
A portable minicomputer for testing a random access memory wherein the memory comprises an array of individual memory chips each containing a multitude of address bits, said portable minicomputer comprising: a central processing unit; an internal memory connected to said central processing unit; means for connecting a memory under test to said central processing unit, said central processing unit including an address counter means for incrementing address lines of said internal memory and said memory under test, and means for generating a plurality of test words; means for writing said test words into said internal memory and said memory under test; means for reading said test words out of said internal memory and said memory under test after said address counter means reaches a predetermined address count; means for comparing said test words read out of said internal memory and said memory under test, said last mentioned means including a fault display indicating a discrepancy between test word bits; and fault conversion means comprising a table of fault display indicia and memory chip addresses for converting a discrepancy identified by said fault display into the address bit location of an individual memory chip in said memory under test.
Claim 3
Dependent Claim
36 words
The portable minicomputer according to claim 1, wherein said means for generating a plurality of test words includes a first test word generator comprising noninverting buffer amplifiers connected to the input of said address counter means.
Claim 4
Dependent Claim
134 words
The portable minicomputer according to claim 2, wherein said means for generating a plurality of test words includes second and third test word generators comprising a plurality of microswitches and shift registers, and a test word selector circuit means, said microswitches programmed to provide a preselected series of pulses to the input of said shift registers, said means further including a first plurality of multiplexers connected to the output of said registers, and wherein certain of the outputs of said registers have inverters connected between the outputs of the registers and the multiplexers, the outputs of said multiplexers selectivity producing the inverted or noninverted outputs of said shift registers as the second and third test words as a result of a control signal from said test word selector circuit means applied to said multiplexers.
Claim 5
Dependent Claim
137 words
The portable minicomputer according to claim 3, wherein said means for generating a plurality of test words includes fourth, fifth, sixth and seventh test word generators comprising a NAND gate, a plurality of inverting and noninverting gates, and a second plurality of multiplexers, the input of said NAND gate connected to a least significant bit output of said address counter means and to said test word selector circuit means, the output of said NAND gate connected through parallel banks of said inverting and noninverting gates to the inputs of said second plurality of multiplexers, the outputs of said last mentioned multiplexers selectively producing said fourth, fifth, sixth and seventh test words as a result of a control signal from said test word selector circuit means applied to said NAND gate and to said second plurality of multiplexers.
Claim 6
Dependent Claim
45 words
The portable minicomputer according to claim 4, wherein said test word selector circuit means includes a binary counter connected to a multiplexer, the output of said multiplexer producing a plurality of control signals which energize the seven test word generator means in a sequential manner.
Claim 7
Dependent Claim
36 words
The portable minicomputer according to claim 5, wherein said means for comparing said test words includes a plurality of exclusive OR gates connected to the data outputs of said memory under test and the internal memory.
Claim 8
Dependent Claim
52 words
The portable minicomputer according to claim 6, wherein said fault display includes data latches connected to the outputs of said exclusive OR gates, and to said address counter means, and operative to inhibit said address counter means if the outputs of said exclusive OR gates indicate any discrepancies in test word data.
Claim 9
Dependent Claim
50 words
The portable minicomputer according to claim 7, wherein said fault display further includes a digital display readout connected to said data latches, said digital display readout including a light emitting diode connected to each data latch to provide a visual indication of the particular exclusive OR gate showing a discrepancy.
Claim 10
Dependent Claim
24 words
The portable minicomputer according to claim 5, further including a source of clock signals to drive said address counter means and said binary counter.
Claim 11
Dependent Claim
18 words
The portable minicomputer according to claim 9 wherein said clock signals are between 10 KHz and 6 MHz.
Claim 12
Dependent Claim
69 words
The portable minicomputer according to claim 1, wherein said internal memory includes two sets of 1K by 1 bit RAM chips, said address counter means producing a signal for enabling one set of RAM chips in the write mode during a first portion of said predetermined address count, and enabling the other set of RAM chips in the write mode during a remaining portion of said predetermined address count.
Claim 13
Dependent Claim
83 words
The portable minicomputer according to claim 1, wherein said means for writing and said means for reading test words into and out of the internal memory and the memory under test includes a write/read circuit comprising a binary counter connected to a multiplexer, the output of the multiplexer connected to a plurality of buffer amplifier means, said buffer amplifier means connected to the internal memory and the memory under test and producing logic signals for controlling write and read functions of the memories.
Claim 14
Dependent Claim
31 words
The portable minicomputer according to claim 12, wherein said write/read circuit further includes timing circuit means for producing write and read pulses for the internal memory and the memory under test.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-16 | 1989-06-17 | 1989-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-16 | 1993-06-17 | 1993-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-16 | 1997-06-17 | 1997-12-17 | $7700.00 | Window Closed / Lapsed |