Large capacity memory circuit with improved write control circuit

Claim 2

A memory circuit comprising first and second bit lines, a plurality of word lines intersecting with said bit lines, a plurality of memory cells arranged at the intersections of said bit lines and word lines, a bus line, a sense amplifier having first and second input nodes, first switching means coupled between said first bit line and said first input node, second switching means coupled between said second bit line and said second input node, third switching means coupled between said bus line and said second input node, first means for operatively enabling said first switching means, second means for operatively enabling said second switching means, third means for selectively enabling said third switching means, and means for controlling said first means, second means and third means such that said second and third switching means are first enabled to determine the state of said sense amplifier by an input signal applied through said bus line with the first switching means disenabled during a single write operation and thereafter said first switching means is enabled to determine the level of said first bit line by said sense amplifier during said single write operation.

Claim 3

The memory circuit according to claim 1, in which each of said first to third switching means includes a field effect transistor.

Claim 4

The memory circuit according to claim 1, in which said sense amplifier includes a control node, a first field effect transistor coupled between said first input node and said control node and having a gate coupled to said second input node, and a second field effect transistor coupled between said second input node and said control node.

Claim 5

The memory circuit according to claim 1, further comprising an output amplifier coupled to said bus line.

Claim 6

A memory circuit comprising first and second memory arrays disposed adjacent to each other, each of said first and second memory arrays including a bus line, a plurality of sense amplifiers each having first and second input nodes, a plurality of bit line pairs, each of said bit line pairs being provided for each of said sense amplifiers and including first and second bit lines, a plurality of first switching means each coupled between the first input node of each sense amplifier and first bit line of the associated bit line pair, a plurality of second switching means each coupled between the second input node of each sense amplifier and said bus line, a plurality of word lines intersecting with said bit lines, and a plurality of memory cells each coupled to one of said word lines and one of said digit lines, a plurality of impedance means each coupled between the second input node of each of said sense amplifiers and the second bit line of the associated bit line pair, means for making said impedance means at a low impedance state during a first period in a write mode to thereby determine the state of the sense amplifier by the level of the second bit line of the associated bit line pair, and means for disenabling said first switching means during said first period and enabling said first switching means during a subsequent second period in the write mode so that the level of the first bit line of the associated bit line pair is determined by the associated sense amplifier.

Claim 7

A memory circuit comprising first and second memory arrays disposed adjacent to each other, each of said first and second memory arrays including a bus line, a plurality of sense amplifiers each having first and second input nodes, a plurality of bit line pairs, each of said bit line pairs being provided for each of said sense amplifiers and including first and second bit lines, a plurality of first switching means each coupled between the first input node of each sense amplifier and first bit line of the associated bit line pair, a plurality of second switching means each coupled between the second input node of each sense amplifier and said bus line, a plurality of word lines intersecting with said bit lines, and a plurality of memory cells each coupled to one of said word lines and one of said digit lines, a plurality of impedance means each coupled between the second input node of each of said sense amplifiers and the second bit line of the associated bit line pair, means for making said impedance means at a low impedance state during a first period in a write mode to thereby determine the state of the sense amplifier by the level of the second bit line of the associated bit line pair, and means for disenabling said first switching means during said first period and enabling said first switching means during a subsequent second period in the write mode so that the level of the first bit line of the associated bit line pair is determined by the associated sense amplifier.

Claim 8

The memory circuit according to claim 5, further comprising first and second reference signal generators coupled to the bus lines of said first and second memory arrays, respectively.

Claim 9

The memory circuit according to claim 6, further comprising a main amplifier coupled to said bus lines of said first and second arrays.

Claim 10

A memory circuit comprising first and second bit lines, a plurality of word lines intersecting with said bit lines, a plurality of memory cells arranged at the intersections of said word lines and said bit lines, a sense amplifier having first and second input nodes, a first field effect transistor coupled between said first bit line and said first input node, a second field effect transistor coupled between said second bit line and said second input node, a bus line, a third field effect transistor coupled between said bus line and said second bit line, means for operatively conducting said third transistor thereby to provide an electrical path between said bus line and said second input node, means for setting a conductance of said second field effect transistor at a small value during a first period in a read or write operation, and means for controlling said first transistor so as to operatively isolate said first bit line from said first input node during said first period and to connect said first bit line to said first node during a subsequent second period in the same read or write operation.

Claim 11

A memory circuit comprising first and second bit lines, a plurality of word lines intersecting with said bit lines, a plurality of memory cells arranged at the intersections of said word lines and said bit lines, a sense amplifier having first and second input nodes, a first field effect transistor coupled between said first bit line and said first input node, a second field effect transistor coupled between said second bit line and said second input node, a bus line, a third field effect transistor coupled between said bus line and said second bit line, means for operatively conducting said third transistor thereby to provide an electrical path between said bus line and said second input node, means for setting a conductance of said second field effect transistor at a small value during a first period in a read or write operation, and means for controlling said first transistor so as to operatively isolate said first bit line from said first input node during said first period and to connect said first bit line to said first node during a subsequent second period in the same read or write operation.

Claim 12

The memory circuit according to claim 8, further comprising a main amplifier having a first input terminal coupled to said bus line and a second input terminal and a reference signal generator coupled to said second input terminal and operatively generating a reference signal.