Patent US4221006A successfully refreshed from Google Patents.
Patent US4558457A successfully refreshed from Google Patents.
US4558457A
Expired / Lapsed
US
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Counter circuit having improved output response
Assignee: Pioneer Corp
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Filing: 1983-11-01
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Granted: 1985-12-10
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Expires: 2003-11-01
Abstract
Abstract An improved clock circuit in which a counter can begin its counting operation following the release of the reset signal always within one-half of the period of the input clock signal. The input clock signal is applied through a D-type flip-flop to one input of an exclusive-OR gate, and to the other input of the exclusive-OR gate directly. The output of the exclusive-OR gate drives the clock input to the counter. The clock input to the D-type flip-flop is supplied by the reset signal.
Inventors
- 👤 Toshio Tabata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:59
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/38
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
99 words
An improved counter circuit in which a counter can begin its counting operation following the release of a reset signal within one half of the period of an input clock signal, comprising, an exclusive-OR gate coupled directly to an input clock signal, a counter, coupled to an output of said exclusive-OR gate, a flip-flop circuit having an input reset signal coupled to the counter through said flip-flop circuit, wherein said input clock signal is also inputted into said flip-flop circuit, and wherein an output signal from said flip-flop circuit is supplied as a gate signal for said exclusive-OR gate.
Claim 2
Dependent Claim
99 words
An improved counter circuit in which a counter can begin its counting operation following the release of a reset signal within one half of the period of an input clock signal, comprising, an exclusive-OR gate coupled directly to an input clock signal, a counter, coupled to an output of said exclusive-OR gate, a flip-flop circuit having an input reset signal coupled to the counter through said flip-flop circuit, wherein said input clock signal is also inputted into said flip-flop circuit, and wherein an output signal from said flip-flop circuit is supplied as a gate signal for said exclusive-OR gate.
Claim 3
Dependent Claim
117 words
An improved counter circuit in which a counter can begin its counting operation following the release of a reset signal within one half of the period of an input clock signal, comprising: a counter having a reset terminal coupled to a reset signal line; a D-type flip-flop circuit having a D input coupled to a clock line signal; an inverter having an input coupled to said reset signal line and an output coupled to a clock input of said flip-flop circuit; and an exclusive-OR gate having a first input coupled to said clock line, a second input coupled to a Q output of said flip-flop circuit, and an output coupled to a clock terminal of said counter.
Claim 4
Dependent Claim
117 words
An improved counter circuit in which a counter can begin its counting operation following the release of a reset signal within one half of the period of an input clock signal, comprising: a counter having a reset terminal coupled to a reset signal line; a D-type flip-flop circuit having a D input coupled to a clock line signal; an inverter having an input coupled to said reset signal line and an output coupled to a clock input of said flip-flop circuit; and an exclusive-OR gate having a first input coupled to said clock line, a second input coupled to a Q output of said flip-flop circuit, and an output coupled to a clock terminal of said counter.
Claim 5
Dependent Claim
106 words
An improved counter circuit in which a counter can begin its counting operation following the release of a reset signal within one half of the period of an input clock signal, comprising: a counter having a reset terminal coupled to a reset signal line; a D-type flip-flop circuit having a clock input terminal coupled to said reset signal line and a D input coupled to a clock signal line; and an exclusive-OR gate having a first input coupled to said clock line, a second input coupled to a Q output of said flip-flop circuit, and an output coupled to a clock input terminal of said counter.
Claim 6
Dependent Claim
106 words
An improved counter circuit in which a counter can begin its counting operation following the release of a reset signal within one half of the period of an input clock signal, comprising: a counter having a reset terminal coupled to a reset signal line; a D-type flip-flop circuit having a clock input terminal coupled to said reset signal line and a D input coupled to a clock signal line; and an exclusive-OR gate having a first input coupled to said clock line, a second input coupled to a Q output of said flip-flop circuit, and an output coupled to a clock input terminal of said counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-09 | 1989-06-10 | 1989-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-09 | 1993-06-10 | 1993-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-09 | 1997-06-10 | 1997-12-10 | $7700.00 | Window Closed / Lapsed |