Apparatus for generating pulse width modulated waves

Claim 1

An apparatus for generating a pulse width modulated wave comprising: a first shift register including a plurality of serially connected binary memory stages for sequentially shifting an input data item in synchronism with a first clock pulse, said first shift register including feedback means for feeding back the outputs of selected ones of said binary memory stages as said input data item to the input of said first binary memory stage through an exclusive OR circuit; a second shift register including the same number of serially connected binary memory stages as those of said first shift register for sequentially shifting an input data item in synchronism with a second clock pulse which has a frequency lower than said first clock pulse, said second shift register also including feedback means for feeding back the outputs of the same selected binary memory stages of said second shift register as those of said first shift register as said input data item to the input of said first binary memory stage of said second shift register through an another exclusive OR circuit; a comparator which compares the output of each stage of said first shift register with the output of the corresponding stage of said second shift register for producing a coincidence output when all outputs of the stages of said first shift register coincide with the outputs of the corresponding stages of said second shift register; and a flip-flop circuit which is set every time the combination of the outputs of respective stages of first shift register comes into a predetermined state and which is reset by said coincidence output, thereby producing a pulse width modulated wave whose pulse width varies gradually with time.

Claim 2

An apparatus for generating a pulse width modulated wave comprising: a first shift register including a plurality of serially connected binary memory stages for sequentially shifting an input data item in synchronism with a first clock pulse, said first shift register including feedback means for feeding back the outputs of selected ones of said binary memory stages as said input data item to the input of said first binary memory stage through an exclusive OR circuit; a second shift register including the same number of serially connected binary memory stages as those of said first shift register for sequentially shifting an input data item in synchronism with a second clock pulse which has a frequency lower than said first clock pulse, said second shift register also including feedback means for feeding back the outputs of the same selected binary memory stages of said second shift register as those of said first shift register as said input data item to the input of said first binary memory stage of said second shift register through an another exclusive OR circuit; a comparator which compares the output of each stage of said first shift register with the output of the corresponding stage of said second shift register for producing a coincidence output when all outputs of the stages of said first shift register coincide with the outputs of the corresponding stages of said second shift register; and a flip-flop circuit which is set every time the combination of the outputs of respective stages of first shift register comes into a predetermined state and which is reset by said coincidence output, thereby producing a pulse width modulated wave whose pulse width varies gradually with time.

Claim 3

An apparatus for generating a pulse width modulated wave, comprising: a first shift register including a plurality of serially connected binary memory stages for sequentially shifting an input data item in synchronism with a first clock pulse, said first shift register including feedback means for feeding back the outputs of selected ones of said binary memory stages as said input data item to the input of said first binary memory stage through an exclusive OR circuit; a second shift register including the same number of serially connected binary memory stages as those of said first shift register for sequentially shifting an input data item in synchronism with a second clock pulse which has a frequency lower than said first clock pulse, said second shift register also including feedback means for feeding back the outputs of selected ones of said binary memory stages as said input data item to the input of said first binary memory stage of said second shift register through an another exclusive OR circuit; a comparator which compares the outputs of respective stages of said first shift register with the outputs of respective stages of said second shift register for producing a coincidence output when all outputs of the stages of said first shift register coincide with the outputs of the corresponding stages of said second shift register; and a flip-flop circuit which is set every time the combination of the outputs of respective stages of first shift register comes into a predetermined state and which is reset by said coincidence output, thereby producing a pulse width modulated wave whose pulse width varies gradually with time, wherein said first and second shift registers each comprise first to fourth binary memory stages each provided with a data input terminal, a data output terminal and a clock terminal connected to receive said first or second clock pulse; said exclusive OR gate circuit of said first shift register has inputs connected to receive the outputs of the third and fourth memory stages of said first register, the output of said exclusive OR gate circuit being supplied to the input of said first binary memory stage of said first shift register; said other exclusive OR gate circuit of said second shift register has inputs connected to receive the outputs of the third and fourth binary memory stages of said second shift register, the output of said other exclusive OR circuit being supplied to the input of said first binary memory stage of said second shift register; and said first shift register further comprises a NOR gate circuit with inputs connected to receive the outputs of respective binary memory stages of said first shift register and an inverted first clock pulse and an output connected to set said flip-flop circuit.

Claim 4

An apparatus for generating a pulse width modulated wave, comprising: a first shift register including a plurality of serially connected binary memory stages for sequentially shifting an input data item in synchronism with a first clock pulse, said first shift register including feedback means for feeding back the outputs of selected ones of said binary memory stages as said input data item to the input of said first binary memory stage through an exclusive OR circuit; a second shift register including the same number of serially connected binary memory stages as those of said first shift register for sequentially shifting an input data item in synchronism with a second clock pulse which has a frequency lower than said first clock pulse, said second shift register also including feedback means for feeding back the outputs of selected ones of said binary memory stages as said input data item to the input of said first binary memory stage of said second shift register through an another exclusive OR circuit; a comparator which compares the outputs of respective stages of said first shift register with the outputs of respective stages of said second shift register for producing a coincidence output when all outputs of the stages of said first shift register coincide with the outputs of the corresponding stages of said second shift register; and a flip-flop circuit which is set every time the combination of the outputs of respective stages of first shift register comes into a predetermined state and which is reset by said coincidence output, thereby producing a pulse width modulated wave whose pulse width varies gradually with time, wherein said first and second shift registers each comprise first to fourth binary memory stages each provided with a data input terminal, a data output terminal and a clock terminal connected to receive said first or second clock pulse; said exclusive OR gate circuit of said first shift register has inputs connected to receive the outputs of the third and fourth memory stages of said first register, the output of said exclusive OR gate circuit being supplied to the input of said first binary memory stage of said first shift register; said other exclusive OR gate circuit of said second shift register has inputs connected to receive the outputs of the third and fourth binary memory stages of said second shift register, the output of said other exclusive OR circuit being supplied to the input of said first binary memory stage of said second shift register; and said first shift register further comprises a NOR gate circuit with inputs connected to receive the outputs of respective binary memory stages of said first shift register and an inverted first clock pulse and an output connected to set said flip-flop circuit.