Symmetrical diode clamp

Claim 2

A monolithic integrated, symmetrical clamp circuit, comprising: first and second terminals; first circuit means coupled between said first and second terminals and the substrate of the integrated diode clamp circuit, said first circuit means being responsive to the voltage level at said first terminal exceeding the voltage level at said second terminal by a predetermined amount for clamping the voltage level thereat and for shunting a majority of the clamping current through the diode clamp circuit to said substrate; said first circuit means including a first transistor of a first conductivity type having first and second collectors, a base and an emitter, said emitter being coupled to said first terminal, said first collector being coupled to said substrate; and a second transistor of a second conductivity type having a collector, a base and an emitter, said emitter being coupled to said second terminal, said collector and base being interconnected with said base and second collector of said first transistor; and second circuit means coupled between said first and second terminals and the substrate of the integrated diode clamp circuit, said second circuit means being responsive to the voltage level at said second terminal exceeding the voltage level at said first terminal by a predetermined amount for clamping the voltage level thereat and for shunting a majority of the clamping current through the diode clamp circuit to said substrate.

Claim 3

The clamp of claim 1 wherein the area of said first collector of said first transistor is ratioed with respect to the area of said second collector thereof.

Claim 4

The clamp of claim 2 wherein said collector ratio is 3:1.

Claim 5

The clamp of claim 1 or 3 wherein said second circuit means includes: a third transistor of said first conductivity type having first, second collectors, a base and an emitter, said emitter being coupled to said second terminal, said first collector being coupled to said substrate, said second collector and base being interconnected with said collector and base at said second transistor; and a fourth transistor of said second conductivity type having a collector, a base and an emitter, said emitter being coupled to said first terminal, said base and collector being interconnected with said base at second collector of said third transistor.

Claim 6

The clamp of claim 4 wherein the area of said first collector of said third transistor is ratioed with respect to the area of said second collector thereof.

Claim 7

The clamp of claim 5 wherein said collector ratio is 3:1.

Claim 8

A monolithic integrated clamp circuit for clamping the voltage at one terminal with respect to another terminal at a predetermined voltage level, comprising: a substrate formed of a semiconductor material of first conductivity type; an epitaxial layer formed on said substrate of a semiconductor material of second conductivity type, said epitaxial layer being contained in an isolated pocket region; a plurality of regions of semiconductor material of said first conductivity type formed in said epitaxial layer in spaced relationship to one another; at least a first one of said regions being electrically shorted to said substrate; a plurality of regions of semiconductor material of said second conductivity type, at least two of said regions being formed in spaced relationship to each other in a second one of said plurality of regions of said first conductivity type and a third of said regions of said second conductivity type being formed in said epitaxial region; first conductivity means for electrically shorting said third region of said second conductivity type to said second one of said regions of said first conductivity type; second conductive means electrically shorting one of said at least two regions with a third one of said plurality of regions of said first conductivity type to the one terminal, said third one of said regions of first conductivity type being in spaced relationship to said at least one region and said second one of said plurality of regions of said first conductivity type; and third conductive means electrically shorting the other of said at least two regions with a fourth one of said plurality of regions of said first conductivity type to the another terminal, said fourth of said first conductivity type being in spaced relationship to both said at least one region and said second one of said regions of said first conductivity type.

Claim 9

A monolithic integrated clamp circuit for clamping the voltage at one terminal with respect to another terminal at a predetermined voltage level, comprising: a substrate formed of a semiconductor material of first conductivity type; an epitaxial layer formed on said substrate of a semiconductor material of second conductivity type, said epitaxial layer being contained in an isolated pocket region; a plurality of regions of semiconductor material of said first conductivity type formed in said epitaxial layer in spaced relationship to one another; at least a first one of said regions being electrically shorted to said substrate; a plurality of regions of semiconductor material of said second conductivity type, at least two of said regions being formed in spaced relationship to each other in a second one of said plurality of regions of said first conductivity type and a third of said regions of said second conductivity type being formed in said epitaxial region; first conductivity means for electrically shorting said third region of said second conductivity type to said second one of said regions of said first conductivity type; second conductive means electrically shorting one of said at least two regions with a third one of said plurality of regions of said first conductivity type to the one terminal, said third one of said regions of first conductivity type being in spaced relationship to said at least one region and said second one of said plurality of regions of said first conductivity type; and third conductive means electrically shorting the other of said at least two regions with a fourth one of said plurality of regions of said first conductivity type to the another terminal, said fourth of said first conductivity type being in spaced relationship to both said at least one region and said second one of said regions of said first conductivity type.

Claim 10

The clamp circuit of claim 7 wherein said at least one region of said first conductivity type is spaced from and symmetrically surrounds major portions of each of said third and fourth regions of said first conductivity type.

Claim 11

The clamp circuit of claim 8 wherein said second region of said first conductivity type is symmetrically spaced from the remaining portions of said third and fourth regions of said first conductivity type.

Claim 12

The clamp circuit of claim 9 wherein said epitaxial layer, said another one region, and said at least one region surrounding said third region form a transistor of first conductivity type having an emitter coupled to the one terminal, a base and first collector connected together at a first node and a second collector electrically shorted to said substrate.

Claim 13

The claim circuit of claim 10 wherein said epitaxial layer, said another one region, and said at least one region surrounding said fourth region form a transistor of said first conductivity type having an emitter coupled to the another terminal, a base and a first collector connected together at said first node and a second collector electrically shorted to said substrate.

Claim 14

The clamp circuit of claim 11 wherein a first one of said at least two regions of second conductivity type, said another one region of said first conductivity type and said epitaxial layer forming a third transistor of second conductivity type having an emitter coupled to the one terminal and a base and collector connected to said first node.

Claim 15

The clamp circuit of claim 12 wherein the second one of said at least two regions of second conductivity type, said another one region of said first conductivity type and said epitaxial layer form a fourth transistor of second second conductivity type having an emitter coupled to the another terminal, and a base and collector connected to said first node.

Claim 16

In combination with a monolithic integrated NPN differential amplifier stage having first and second inputs, a symmetrical clamping circuit, comprising: first and second terminals said first terminal being coupled to the first input and said second terminal beng coupled to the second input of the NPN amplifier; first circuit means coupled between said first and second terminals and the substrate of the integrated diode clamp circuit, said first circuit means being responsive to the voltage level at said first terminal exceeding the voltage level at said second terminal by a predetermined amount for clamping the voltage level thereat and for shunting a majority of the clamping current through the diode clamp circuit to said substrate, said first circuit means including a first transistor of a first conductivity type having first and second collectors, a base and an emitter, said emitter being coupled to said first terminal, said first collector being coupled to said substrate, and a second transistor of a second conductivity type having a collector, a base and an emitter, said emitter being coupled to said second terminal, said collector and base being interconnected with said base and second collector of said first transistor; and second circuit means coupled between said first and second terminals and the substrate of the integrated diode clamp circuit, said second circuit means being responsive to the voltage level at second terminal exceeding the voltage level at said first terminal by a predetermined amount for clamping the voltage level thereat and for shunting a majority of the clamping current through the diode clamp circuit to said substrate.

Claim 17

In combination with a monolithic integrated NPN differential amplifier stage having first and second inputs, a symmetrical clamping circuit, comprising: first and second terminals said first terminal being coupled to the first input and said second terminal beng coupled to the second input of the NPN amplifier; first circuit means coupled between said first and second terminals and the substrate of the integrated diode clamp circuit, said first circuit means being responsive to the voltage level at said first terminal exceeding the voltage level at said second terminal by a predetermined amount for clamping the voltage level thereat and for shunting a majority of the clamping current through the diode clamp circuit to said substrate, said first circuit means including a first transistor of a first conductivity type having first and second collectors, a base and an emitter, said emitter being coupled to said first terminal, said first collector being coupled to said substrate, and a second transistor of a second conductivity type having a collector, a base and an emitter, said emitter being coupled to said second terminal, said collector and base being interconnected with said base and second collector of said first transistor; and second circuit means coupled between said first and second terminals and the substrate of the integrated diode clamp circuit, said second circuit means being responsive to the voltage level at second terminal exceeding the voltage level at said first terminal by a predetermined amount for clamping the voltage level thereat and for shunting a majority of the clamping current through the diode clamp circuit to said substrate.

Claim 18

The clamp of claim 14 wherein the area of said first collector of said first transistor is ratioed with respect to the area of said second collector thereof.

Claim 19

The clamp of claim 15 wherein said collector ratio is 3:1.

Claim 20

The clamp of claim 14 or 16 wherein said second circuit means includes: a third transistor of said first conductivity type having first, second collectors, a base and an emitter, said emitter being coupled to said second terminal, said first collector being coupled to said substrate, said second collector and base being interconnected with said collector and base at said second transistor; and a fourth transistor of said second conductivity type having a collector, a base and an emitter, said emitter being coupled to said first terminal, said base and collector being interconnected with said base at second collector of said third transistor.

Claim 21

The clamp of claim 17 wherein the area of said first collector of said third transistor is ratioed with respect to the area of said second collector thereof.

Claim 22

The clamp of claim 18 wherein said collector ratio is 3:1.