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US4388632A
Expired / Lapsed
US
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Signal limiting integrated circuit
Assignee: Allegro Microsystems LLC
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Filing: 1980-10-03
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Granted: 1983-06-14
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Expires: 2000-10-03
Abstract
Abstract A simple silicon integrated circuit consists of two identical Schottky diodes formed in epitaxial pockets that are defined by P-N junction isolation walls. Metallization is provided to connect the diodes back-to-back in parallel and to provide terminal pads at the two nodes of the parallel circuit. Another metal film makes contact with the isolation wall and has an enlarged termination pad portion. This component may be connected across the input of an A/D converter to limit input signals to a small value.
Inventors
- 👤 William E. Richardson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:34
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/201; H10D84/204; H10D84/221; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
157 words
A signal limiting integrated circuit comprising a silicon body of one conductivity type, an epitaxial layer on said body being lightly doped with impurities of the opposite conductivity type, an isolation wall through said epitaxial layer being heavily doped with impurities of said one type forming only two pockets of unaltered epitaxial material, only first, second and third metal films overlying said epitaxial layer, said first metal film making Schottky barrier contact to one of said pockets and ohmic contact to the other of said pockets, said second metal film making Schottky barrier contact to said other of said pockets and ohmic contact to said one pocket, each of said first and second metal films having an enlarged termination portion located directly over said pocket to which said Schottky barrier contact is made, said third metal film consisting of an enlarged termination located directly over an enlarged portion of said isolation wall and making ohmic contact thereto.
Claim 2
Dependent Claim
157 words
A signal limiting integrated circuit comprising a silicon body of one conductivity type, an epitaxial layer on said body being lightly doped with impurities of the opposite conductivity type, an isolation wall through said epitaxial layer being heavily doped with impurities of said one type forming only two pockets of unaltered epitaxial material, only first, second and third metal films overlying said epitaxial layer, said first metal film making Schottky barrier contact to one of said pockets and ohmic contact to the other of said pockets, said second metal film making Schottky barrier contact to said other of said pockets and ohmic contact to said one pocket, each of said first and second metal films having an enlarged termination portion located directly over said pocket to which said Schottky barrier contact is made, said third metal film consisting of an enlarged termination located directly over an enlarged portion of said isolation wall and making ohmic contact thereto.
Claim 3
Dependent Claim
21 words
The integrated circuit of claim 1 wherein the area of each said termination pad portion is at least 5000 square microns.
Claim 4
Dependent Claim
37 words
The integrated circuit of claim 1 wherein the area of the p-n junction between said one pocket and said isolation wall is essentially equal to the p-n junction area between said isolation wall and said other pocket.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-13 | 1986-12-13 | 1987-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-13 | 1990-12-13 | 1991-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-13 | 1994-12-13 | 1995-06-14 | $7700.00 | Window Closed / Lapsed |