Patent US3615412A successfully refreshed from Google Patents.
Patent US4558225A successfully refreshed from Google Patents.
US4558225A
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US
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Target body position measuring method for charged particle beam fine pattern exposure system
Assignee: Toshiba Corp
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Filing: 1983-08-29
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Granted: 1985-12-10
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Expires: 2003-08-29
Abstract
Abstract Disclosed is a method for measuring the position of a silicon wafer as a workpiece to be exposed. The method is suitably used in an electron beam exposure system. A wafer has a plurality of chip alignment marks which respectively designate a plurality of chip field areas, included in a dicing line area. When the wafer is contained ion a holder and is fixed in the exposure system, edge portions of the wafer are partially scanned with the electron beam to roughly measure the position of the wafer. In accordance with this wafer position data, a wafer surface portion required for detecting only the marks is defined within the dicing line area. In the mark detection with the electron beam, the electron beam irradiates only the defined wafer surface portion of the wafer surface, thereby providing highly precise measurement of the wafer position and avoiding undesirable irritation of the circuit formation area.
Inventors
- 👤 Mineo Gotou
- 👤 Ryoichi Yoshikawa
- 👤 Toru Tojo
- 👤 Hirotsugu Wada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:53
CPC Classifications
H; H01; H01J; H01J37/00; H01J37/30; H01J37/304; H01J37/3045; H10; H10P; H10P95/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
260 words
A method for measuring the actual position of a semiconductor wafer having a straight edge portion when the water is aligned with a charged particle optical system of a pattern forming apparatus for forming desired fine circuit patterns on the wafer by using a charged particle beam such as an electron beam, said method comprising the steps of: scanning an edge portion of the wafer at plural points including said straight edge portion by said charged particle beam, and obtaining primary wafer position data when the wafer having chip alignment marks is positioned in the pattern forming apparatus, the chip alignment marks being included in a non-circuit area defined between a plurality of chip field areas and corresponding to the plurality of chip field areas, and the fine circuit patterns being formed on the plurality of chip field areas, respectively; defining a surface portion of the semiconductor wafer to be illuminated with the charged particle beam, said wafer surface portion corresponding to the non-circuit area and including the chip alignment marks of the wafer in accordance with the primary wafer position data; radiating the charged particle beam onto the wafer such that the charged particle beam exclusively irradiates an area corresponding to the wafer surface portion defined; scanning the wafer surface portion with the charged particle beam to detect chip alignment marks; and obtaining secondary wafer position data which is more precise than the primary wafer position data in accordance with detected mark data, whereby the actual position of the wafer relative to the electronic optical system is finally measured.
Claim 2
Independent Claim
260 words
A method for measuring the actual position of a semiconductor wafer having a straight edge portion when the water is aligned with a charged particle optical system of a pattern forming apparatus for forming desired fine circuit patterns on the wafer by using a charged particle beam such as an electron beam, said method comprising the steps of: scanning an edge portion of the wafer at plural points including said straight edge portion by said charged particle beam, and obtaining primary wafer position data when the wafer having chip alignment marks is positioned in the pattern forming apparatus, the chip alignment marks being included in a non-circuit area defined between a plurality of chip field areas and corresponding to the plurality of chip field areas, and the fine circuit patterns being formed on the plurality of chip field areas, respectively; defining a surface portion of the semiconductor wafer to be illuminated with the charged particle beam, said wafer surface portion corresponding to the non-circuit area and including the chip alignment marks of the wafer in accordance with the primary wafer position data; radiating the charged particle beam onto the wafer such that the charged particle beam exclusively irradiates an area corresponding to the wafer surface portion defined; scanning the wafer surface portion with the charged particle beam to detect chip alignment marks; and obtaining secondary wafer position data which is more precise than the primary wafer position data in accordance with detected mark data, whereby the actual position of the wafer relative to the electronic optical system is finally measured.
Claim 3
Dependent Claim
42 words
The method according to claim 1, wherein said wafer is scanned by the charged particle beams at plural points of the straight edge portion and at plural points of an arcuated edge portion, in said step of obtaining the primary position data.
Claim 4
Dependent Claim
92 words
The method according to claim 2, wherein said primary position data obtaining step comprises the step of partially radiating the electron beam onto the straight edge portion of the wafer through a plurality of openings formed in a flat plate portion of a wafer holding member which overlaps with a periphery of the wafer, the wafer holding member being provided to hold the wafer having a substantially disk liked shape and the straight edge portion and being positioned on a workpiece table, thereby scanning the straight edge portion with the electron beam.
Claim 5
Dependent Claim
57 words
The method according to claim 3, wherein said primary position data obtaining step comprises the step of radiating the electron beam onto at least one position of the arcuated edge portion through at least one opening formed in the flat plate portion of the wafer holding member, thereby scanning the arcuated edge portion with the electron beam.
Claim 6
Dependent Claim
82 words
The method according to claim 2, wherein said beam illumination surface portion defining step comprises the step of computing the wafer surface portion defined which includes the chip alignment marks included in the dicing line area, which is formed on the wafer to define the plurality of chip field areas and to serve as the non-circuit area, so as to respectively designate the plurality of chip field areas, said target body surface portion being prevented from deviating from the dicing line area.
Claim 7
Dependent Claim
82 words
The method according to claim 4, wherein said beam illumination surface portion defining step comprises the step of computing the wafer surface portion defined which includes the chip alignment marks included in the dicing line area, which is formed on the wafer to define the plurality of chip field areas and to serve as the non-circuit area, so as to respectively designate the plurality of chip field areas, said wafer surface portion being prevented from being deviated from the dicing line area.
Claim 8
Dependent Claim
44 words
The method according to claim 5, wherein the primary semiconductor wafer position data includes edge position data of the wafer which is obtained in accordance with reflected electron beams reflected by the straight edge portion of the wafer and the arcuated edge portion thereof.
Claim 9
Dependent Claim
47 words
The method according to claim 7, wherein the wafer surface portion defined is computed solely on the basis of a determined positional relationship between the edge position data and the chip alignment marks in accordance with a predetermined algorithm, using the edge position data as input data.
Claim 10
Dependent Claim
44 words
The method according to claim 6, wherein the primary semiconductor wafer position data includes edge position data of the wafer which is obtained in accordance with reflected electron beams reflected by the straight edge portion of the wafer and the arcuated edge portion thereof.
Claim 11
Dependent Claim
48 words
The method according to claim 9, wherein the semiconductor wafer surface portion defined is computed solely on the basis of a determined positional relationship between the edge position data and the chip alignment marks in accordance with a predetermined algorithm, using the edge position data as input data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-09 | 1989-06-10 | 1989-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-09 | 1993-06-10 | 1993-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-09 | 1997-06-10 | 1997-12-10 | $7700.00 | Window Closed / Lapsed |