Patent US4553107A successfully refreshed from Google Patents.
US4553107A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror circuit having stabilized output current
Assignee: Toshiba Corp
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Filing: 1983-12-02
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Granted: 1985-11-12
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Expires: 2003-12-02
Abstract
Abstract A current mirror circuit having a good input-output current characteristic and operable by a relatively small power supply voltage. The current mirror circuit includes a first resistor connected to a current input circuit, a first transistor whose emitter is connected to the junction of the first resistor and the current input circuit, means for providing a voltage offset, a second resistor connected in series with the base of the first transistor through the voltage offset providing means, a first constant current source connected to the collector of the first transistor, a second constant current source connected to the junction of the base of the first transistor and the voltage offset providing means, and a second transistor whose base is connected to the collector of the first transistor and whose emitter is connected to the junction of the voltage offset providing means and the second resistor to provide a feedback loop. The output current of the current mirror circuit is taken from the collector of the second transistor.
Inventors
- 👤 Atsushi Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:56
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/30; H03F3/3083; H03F3/3086; H03F3/3093
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
184 words
A current mirror circuit responsive to a current input comprising: a first impedance path connected to said current input to receive an input current; a first transistor whose emitter is connected to a junction of said first impedance path and said current input; means for providing a voltage offset equivalent to the base-emitter voltage of said first transistor connected to the base of said first transistor; a second impedance path connected in series with said voltage offset providing means; a first current source connected to the collector of said first transistor for producing a first current of substantially constant value; a second current source connected to said voltage offset providing means for producing a second current of substantially constant value; and a second transistor whose base is connected to the collector of said first transistor, whose collector is connected to a current output, and whose emitter is connected solely and directly to the junction of said voltage offset providing means and said second impedance path for producing a feedback loop to output a collector current which is substantially linearly related to said current input.
Claim 2
Dependent Claim
184 words
A current mirror circuit responsive to a current input comprising: a first impedance path connected to said current input to receive an input current; a first transistor whose emitter is connected to a junction of said first impedance path and said current input; means for providing a voltage offset equivalent to the base-emitter voltage of said first transistor connected to the base of said first transistor; a second impedance path connected in series with said voltage offset providing means; a first current source connected to the collector of said first transistor for producing a first current of substantially constant value; a second current source connected to said voltage offset providing means for producing a second current of substantially constant value; and a second transistor whose base is connected to the collector of said first transistor, whose collector is connected to a current output, and whose emitter is connected solely and directly to the junction of said voltage offset providing means and said second impedance path for producing a feedback loop to output a collector current which is substantially linearly related to said current input.
Claim 3
Dependent Claim
19 words
The current mirror circuit according to claim 1, wherein said voltage offset providing means is a diode junction means.
Claim 4
Dependent Claim
16 words
The current mirror circuit according to claim 2, wherein said diode junction means is a diode.
Claim 5
Dependent Claim
21 words
The current mirror circuit according to claim 2, wherein said diode junction means is a third transistor connected in diode fashion.
Claim 6
Dependent Claim
31 words
The current mirror circuit according to claim 4, wherein said third transistor connected in diode fashion has an emitter of different area than that of the emitter of said first transistor.
Claim 7
Dependent Claim
30 words
The current mirror circuit according to claim 5, wherein said third transistor connected in diode fashion has an emitter area larger than that of the emitter of said first transistor.
Claim 8
Dependent Claim
27 words
The current mirror circuit according to claim 5, wherein said third transistor connected in diode fashion has an emitter area lesser than that of said first transistor.
Claim 9
Dependent Claim
17 words
The current mirror circuit according to claim 3 wherein said first and second impedance paths comprise resistors.
Claim 10
Dependent Claim
235 words
A current mirror circuit responsive to a current input comprising: a first impedance path connected to said current input to receive an input current; a first transistor whose emitter is connected to a junction of said first impedance path and said current input; means for providing a voltage offset equivalent to the base-emitter voltage of said first transistor connected to the base of said first transistor; a second impedance path connected in series with said voltage offset providing means; a first current source connected to the collector of said first transistor for producing a first current of substantially constant value; a second current source connected to said voltage offset providing means for producing a second current of substantially constant value; a second transistor whose base is connected to the collector of said first transistor, whose collector is connected to a current output, and whose emitter is connected to a junction of said voltage offset providing means and said second impedance path for producing a feedback loop to output a collector current which is substantially linearly related to said current input; said voltage offset providing means comprising a third transistor connected at its collector-emitter path between said second impedance path and said second constant current source and at its base to the base of said first transistor; and a fourth transistor whose base-emitter path is connected in parallel with the collector-base path of said third transistor.
Claim 11
Dependent Claim
235 words
A current mirror circuit responsive to a current input comprising: a first impedance path connected to said current input to receive an input current; a first transistor whose emitter is connected to a junction of said first impedance path and said current input; means for providing a voltage offset equivalent to the base-emitter voltage of said first transistor connected to the base of said first transistor; a second impedance path connected in series with said voltage offset providing means; a first current source connected to the collector of said first transistor for producing a first current of substantially constant value; a second current source connected to said voltage offset providing means for producing a second current of substantially constant value; a second transistor whose base is connected to the collector of said first transistor, whose collector is connected to a current output, and whose emitter is connected to a junction of said voltage offset providing means and said second impedance path for producing a feedback loop to output a collector current which is substantially linearly related to said current input; said voltage offset providing means comprising a third transistor connected at its collector-emitter path between said second impedance path and said second constant current source and at its base to the base of said first transistor; and a fourth transistor whose base-emitter path is connected in parallel with the collector-base path of said third transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-11 | 1989-05-13 | 1989-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-11 | 1993-05-13 | 1993-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-11 | 1997-05-13 | 1997-11-12 | $7700.00 | Window Closed / Lapsed |