US4410859A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal amplifier circuit arrangement with output current limiting function
Assignee: Toshiba Corp
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Filing: 1981-10-30
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Granted: 1983-10-18
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Expires: 2001-10-30
Abstract
Abstract A signal amplifier circuit arrangement includes an input amplifying circuit having a current mirror load circuit and an output transistor having its base connected to the output of the input amplifying circuit, its collector connected to the output terminal of the signal amplifying circuit and its emitter connected to a power supply terminal. In the signal amplifier circuit arrangement a current detection resistor is connected between the emitter of the output transistor and the power supply terminal and a diode is connected between the emitter or collector of the output transistor and the collector of a diode-connected transistor of the current mirror circuit. When a large current flows through the output transistor due to the short-circuiting of the output terminal, the diode connected in series with the emitter-base path of a transistor in the current mirror circuit is rendered conductive by a voltage drop developed across the current detection resistor, thus providing a current negative feedback to the base of the output transistor through the current mirror circuit for restricting the collector current of the output transistor.
Inventors
- 👤 Hisao Kuwahara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:14
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/4508; H03F3/45085; H03F1/00; H03F1/52; H03G; H03G11/00; H03G11/02; H03F2203/00; H03F2203/45; H03F2203/45598; H03F2203/45601; H03F2203/45604; H03F2203/45664; H03F2203/45674
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
219 words
A signal amplifier circuit arrangement comprising: an input amplifying circuit having a current mirror load circuit comprised of first and second transistors of a first conductivity type each having an emitter, collector and base, said emitters of said first and second transistors being connected to a power supply terminal, said bases of said first and second transistors connected to each other and said collector of said second transistor being coupled to said base of said second transistor; output transistor means having first, second and third terminals respectively corresponding to emitter, collector and base of a transistor of the first conductivity type, said third terminal of said output transistor means being connected to said collector of said first transistor and said second terminal of said output transistor means being connected to an output terminal of said signal amplifying circuit to be connected to a load; a current detection resistance element connected between said first terminal of said output transistor means and said power supply terminal; and a diode means connected between said collector of said second transistor and said first terminal of said output transistor means, said diode means being rendered conductive when a voltage drop across said current detection resistance element is greater than a sum of emitter-base voltage of said first transistor and cut-in voltage of said diode.
Claim 2
Dependent Claim
219 words
A signal amplifier circuit arrangement comprising: an input amplifying circuit having a current mirror load circuit comprised of first and second transistors of a first conductivity type each having an emitter, collector and base, said emitters of said first and second transistors being connected to a power supply terminal, said bases of said first and second transistors connected to each other and said collector of said second transistor being coupled to said base of said second transistor; output transistor means having first, second and third terminals respectively corresponding to emitter, collector and base of a transistor of the first conductivity type, said third terminal of said output transistor means being connected to said collector of said first transistor and said second terminal of said output transistor means being connected to an output terminal of said signal amplifying circuit to be connected to a load; a current detection resistance element connected between said first terminal of said output transistor means and said power supply terminal; and a diode means connected between said collector of said second transistor and said first terminal of said output transistor means, said diode means being rendered conductive when a voltage drop across said current detection resistance element is greater than a sum of emitter-base voltage of said first transistor and cut-in voltage of said diode.
Claim 3
Dependent Claim
20 words
A signal amplifier circuit arrangement according to claim 1, in which said input amplifying circuit is a differential amplifier circuit.
Claim 4
Dependent Claim
53 words
A signal amplifier circuit arrangement according to claim 2, in which a first input of said differential amplifier circuit is connected to receive a signal to be amplified and a second input of said differential amplifier circuit is connected to said output terminal of said signal amplifier circuit through a negative feedback circuit.
Claim 5
Dependent Claim
94 words
A signal amplifier circuit arrangement according to claim 1, in which said output transistor means includes a third transistor of said first conductivity type and a fourth transistor of a second conductivity type, said third transistor having its base connected to said collector of said first transistor, its emitter connected to said current detection resistance element and its collector connected to a base of said fourth transistor, and said fourth transistor having its collector connected to said current detection resistance element and its emitter connected to said output terminal of said signal amplifier circuit.
Claim 6
Dependent Claim
90 words
A signal amplifier circuit arrangement according to claim 1, said output transistor means includes a third transistor of said first conductivity type and fourth transistor of a second conductivity type, said third transistor having its base connected to said collector of said first transistor, its emitter connected to said power supply terminal and its collector connected to a base of said fourth transistor, and said fourth transistor having its collector connected to said current detection resistance element and its emitter connected to said output terminal of said signal amplifier circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-17 | 1987-04-18 | 1987-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-17 | 1991-04-18 | 1991-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-17 | 1995-04-18 | 1995-10-18 | $7700.00 | Window Closed / Lapsed |