Pulse corrector for phase comparator inputs

Claim 2

Pulse corrector which in response to first and second input pulses applied to its first and second inputs provides first and second output pulses at its first and second outputs respectively, the first pulse edge occurring at said first output after an interruption of said first input pulses never leading the corresponding first pulse edge occurring at said second output irrespective of the phase relationship between the corresponding first pulse edges occurring at said inputs after said interruption, characterized in that the duration of the pulse (TL) produced at said first output, and starting with said first pulse edge occurring at said first output after said interruption is not substantially less than that of one (S4) of said first (T) and second (S) input pulses.

Claim 3

Pulse corrector according to claim 1, characterized in that said second output pulses (V) are only dependent on and synchronous with said second input pulses (S) which are not interrupted when said first input pulses are interrupted.

Claim 4

Pulse corrector according to claim 2, characterized in that said pulse duration (TL) is not substantially less than that of one (S4,S4) of said synchronous second input (S) and output (V) pulses, said one second output pulse (S4) starting with said first edge which substantially coincides with the first edge of said one second input pulse (S4).

Claim 5

Pulse corrector according to claim 3, characterized in that it includes counting means (SR) producing said first edge of said one second output pulse (S4) when having counted a predetermined number of edges of said second input pulses (S) after the end of said interruption of said first input pulses (T).

Claim 6

Pulse corrector according to claim 4, characterized in that it includes a retriggerable monostable circuit (RMS) having an input constituted by said first pulse corrector input and an output coupled to the data (D) and reset (R) inputs of a shift register (SR) which constitutes said counting means and further has a clock input (S) coupled to said second pulse corrector input and an output (QD) coupled to logic means (JKFF, DFF, G1, G2, OR, INV1) able to produce at said first pulse corrector output said pulse starting with said first pulse edge occurring at said first output after said interruption, the operation of said logic means being started when said monostable circuit (RMS) has detected the re-appearance of first input pulses at the end of said interruption and when said shift register has counted said predetermined number of edges of said second input pulses and has accordingly activated its said ouput (QD).

Claim 7

Pulse corrector according to claim 5, characterized in that said logic means include first memory means (JKFF), second memory means (DFF) and gating means (G1, G2, OR), said first memory means (JKFF) being able to register said activated condition of said shift register output (QD) under the control of an edge (S4↓) of said second input pulses following said counted predetermined number, said second memory means (DFF) being coupled to an output (Q1) of said first memory means (JKFF) and being able to store the registered condition (Q1) of said first memory means (JKFF) under the control of an edge (T5↑) of said first input pulses (T) following said following edge (S4↓) of said second input pulses, and said gating means (G1, G2, OR, INV1) being coupled to outputs (QD, Q1, Q2) and said shift register and of said first and second memory means and to said first pulse corrector input (T) and having an output coupled to said first pulse corrector output (R), said gating means producing a first output signal R=QD.Q.sub.1 ·Q.sub.2.T wherein: QD is said condition of said shift register output; Q 1 is an output of said first memory means; Q 2 is an output of said second memory means; T is said first pulse corrector input.

Claim 8

Pulse corrector according to claim 6, characterized in that said first memory means is a JK-flipflop (JKFF) having a J-input coupled to said shift register output (QD), a clock input (C) coupled to said second pulse corrector input and an output (Q1) which together with said shift register output (QD) is coupled to a first gating circuit (G1) which forms part of said gating means and has an output coupled to said first pulse corrector output (R).

Claim 9

Pulse corrector according to claim 6, characterized in that said second memory means is a D-flipflop (DFF) having a clock input (C) coupled to said first pulse corrector input and an output (Q2) which together with said first pulse corrector input is coupled to a second gating circuit (G2) which also forms part of said gating means and has an output coupled to said first pulse corrector output (R).

Claim 10

Pulse corrector according to claim 1, characterized in that said second pulse corrector input is connected to said second pulse corrector output via an inverter (INV2).

Claim 11

Pulse corrector according to claim 1 characterized in that it forms part of a phaselocked loop (PLL) which further includes a digital phase detector (DPD) having two inputs (R, V) coupled to said outputs of said pulse corrector (PC) and two outputs (PU, PD) coupled to a controller oscillator providing said second output pulses (V) at its output which is coupled to said second input of said pulse corrector to the first input of which said first input pulses are applied from a reference source.

Claim 12

Phase detector arrangement including a pulse corrector with first and second inputs and with first and second outputs coupled to first and second inputs of a digital phase detector, said pulse corrector in response to first and second input pulses applied to said first and second inputs providing first and second output pulses at said first and second outputs respectively, the first pulse edge of a first pulse occurring at said first output after an interruption of said first input pulses never leading the corresponding first pulse edge occurring at said second output irrespective of the phase relationship between the corresponding first pulse edges occurring at said inputs after said interruption, characterized in that said pulse corrector (PC) includes counting means (SR) producing said corresponding first pulse edge at said second output when having counted a predetermined number of edges of said second input pulses (S) after the end of said interruption of said first input pulses (T) and characterized in that it includes a retriggerable monostable circuit (RMS) having an input constituted by said first pulse corrector input and an output coupled to the data (D) and reset (R) inputs of a shift register (SR) which constitutes said counting means and further has a clock input (S) coupled to said second pulse corrector input and an output (QD) coupled to logic means (JKFF, DFF, G1, G2, OR, INV1) able to produce at said first pulse corrector output said pulse starting with said first pulse edge occurring at said first output after said interruption, the operation of said logic means being started when said monostable circuit (RMS) has detected the re-appearance of first input pulses at the end of said interruption and when said shift register has counted said predetermined number of edges of said second input pulses and has accordingly activated its said output (QD).

Claim 13

Phase detector arrangement including a pulse corrector with first and second inputs and with first and second outputs coupled to first and second inputs of a digital phase detector, said pulse corrector in response to first and second input pulses applied to said first and second inputs providing first and second output pulses at said first and second outputs respectively, the first pulse edge of a first pulse occurring at said first output after an interruption of said first input pulses never leading the corresponding first pulse edge occurring at said second output irrespective of the phase relationship between the corresponding first pulse edges occurring at said inputs after said interruption, characterized in that said pulse corrector (PC) includes counting means (SR) producing said corresponding first pulse edge at said second output when having counted a predetermined number of edges of said second input pulses (S) after the end of said interruption of said first input pulses (T) and characterized in that it includes a retriggerable monostable circuit (RMS) having an input constituted by said first pulse corrector input and an output coupled to the data (D) and reset (R) inputs of a shift register (SR) which constitutes said counting means and further has a clock input (S) coupled to said second pulse corrector input and an output (QD) coupled to logic means (JKFF, DFF, G1, G2, OR, INV1) able to produce at said first pulse corrector output said pulse starting with said first pulse edge occurring at said first output after said interruption, the operation of said logic means being started when said monostable circuit (RMS) has detected the re-appearance of first input pulses at the end of said interruption and when said shift register has counted said predetermined number of edges of said second input pulses and has accordingly activated its said output (QD).