Digital processing circuit having a multiplication function

Claim 2

A digital processing circuit for multiplying a multiplicand and a multiplier to produce a multiplication result, comprising: first means for storing said multiplicand therein; second means for storing said multiplier therein; third means coupled to said second means for decoding the multiplier read out of said second means according to Booth's algorithm to thereby produce coefficients; fourth means coupled to said third means and said first means for producing partial products by multiplying the multiplicand by said coefficients; fifth means for receiving first and second inputs and for executing addition of said first and second inputs, said first input comprising said partial products; sixth means for receiving an addition result from said fifth means and feeding back this result as said second input of said fifth means; and seventh means for outputting said addition result as a multiplication result.

Claim 3

A digital processing circuit as claimed in claim 1, wherein said multiplier has a plurality of bits, and each coefficient produced by said third means corresponds to a predetermined number of said bits less than said plurality of bits.

Claim 4

A digital processing circuit as claimed in claim 2, wherein each of said coefficients produced by said third means is -2, -1, 0, +1 or +2 in accordance with its corresponding predetermined number of bits.

Claim 5

A digital processing circuit as claimed in claim 1 or 2, wherein said second means comprises a shift-register.

Claim 6

A digital processing circuit as claimed in claim 4, wherein said shift-register serially stores said plurality of bits of said multiplier and serially shifts said plurality of bits to said third means.

Claim 7

A digital processing circuit as claimed in claim 5, further comprising a clock generator generating a first clock having a first frequency for driving at least said sixth means and a second clock having a second frequency higher than said first frequency for driving said second means.

Claim 8

A digital processing circuit as claimed in claim 4, wherein said shift register stores said plurality of bits in parallel and shifts said bits in parallel to said third means.

Claim 9

A digital processing circuit as claimed in claim 4, further comprising a clock generator generating a clock for driving said second means and said sixth means.

Claim 10

A digital processing circuit as claimed in claim 1, wherein said seventh means is coupled to said fifth means.

Claim 11

A digital processing circuit as claimed in claim 1, wherein said seventh means is coupled to said sixth means.

Claim 12

A digital processing circuit for multiplying a multiplicand by a plural bit multiplier to produce a multiplication result, comprising: a first memory for storing said multiplicand; a second memory for storing said multiplier; a decoder for decoding the multiplier in said second memory according to Booth's algorithm to produce coefficients with each coefficient corresponding to a predetermined number of multiplier bits less then the entire number of bits in said multiplier; a partial product producing circuit for producing partial products by multiplying the multiplicand in said first memory by the coefficients produced by said decoder; an adder circuit for adding together the partial products produced by said partial product producing circuit to produce a multiplication result; and means for transferring n consecutive multiplier bits in parallel from said second memory to said decoder, where n is equal to said predetermined number.

Claim 13

A digital processing circuit for multiplying a multiplicand by a plural bit multiplier to produce a multiplication result, comprising: a first memory for storing said multiplicand; a second memory for storing said multiplier; a decoder for decoding the multiplier in said second memory according to Booth's algorithm to produce coefficients with each coefficient corresponding to a predetermined number of multiplier bits less then the entire number of bits in said multiplier; a partial product producing circuit for producing partial products by multiplying the multiplicand in said first memory by the coefficients produced by said decoder; an adder circuit for adding together the partial products produced by said partial product producing circuit to produce a multiplication result; and means for transferring n consecutive multiplier bits in parallel from said second memory to said decoder, where n is equal to said predetermined number.

Claim 14

A digital processing circuit as claimed in claim 11, wherein said second memory comprises two shift-register portions arranged in parallel.

Claim 15

A digital processing circuit as claimed in claim 12, wherein said second memory further comprises delaying means for delaying an output from one of said two shift-register portions.

Claim 16

A digital processing circuit as claimed in claim 13, wherein said decoder produces said coefficients depending on a combination of outputs from said two shift-register portions and said delaying means.

Claim 17

A digital processing circuit as claimed in claim 14, wherein said coefficients are any one of -2, -1, 0, +1 or +2.

Claim 18

A digital processing circuit as claimed in claim 11, 12 or 13, wherein said adder circuit adds the partial product corresponding to each combination of consecutive bits of said multiplier to a sum of previously obtained partial products.

Claim 19

A digital processing circuit as claimed in claim 11, 12 or 13, wherein said adder circuit comprises an adder having a first input receiving said partial product from said partial product producing circuit and a second input, a shift-register receiving an output from said adder, and a register receiving an output from said shift-register and applying its output to said second input of said adder.

Claim 20

A digital processing circuit as claimed in claim 11, wherein said first memory comprises a register having first, second and third inputs and an output and selectively storing any one of said three inputs as said multiplicand in response to a control signal, means for providing initial data as said first input, means for feeding back the output of said register as said second input and means for providing a further partial product sum as said third input, said adder circuit comprising a first adder for adding a plurality of consecutive partial products during a first period of time to produce a first partial product sum and for adding a plurality of consecutive partial products during a second period of time to produce a second partial product sum, and a second adder for adding together the first and second partial product sums to generate a said further partial product sum, and means for generating said control signal to select said first input for the first partial product in said first period of time, said third input for the first partial product in said second period of time and said second input during each of said first and second periods of time after the first partial products.