Data acquisition channel apparatus

Claim 2

Data input channel signal amplifier apparatus comprising: an integrated circuit operational amplifier circuit having positive and negative input terminals and a unitary output terminal; first and second co-mounted bipolar signal preamplifier transistors having base terminals connected to the positive and negative terminals of an input channel differential signal receiving port, collector terminals connected to said negative and positive operational amplifier circuit input terminals respectively and having emitter terminals connected together through a differential signal gain determining impedance member, said emitter terminals being also connected with a pair of co-mounted current source transistors; first and second co-mounted bipolar negative feedback coupling transistors connected between said preamplifier transistors and said co-mounted current source transistors and having collector terminals connected to said preamplifier transistor emitter terminals, emitter terminals connected together through a differential feedback gain determining impedance member and connected also to said co-mounted current source transistors, and having base terminals connected with a zero signal reference node and with said operational amplifier output node respectively through resistor divider networks; and a source of temperature modulated bias signal coupled with said first and second negative feedback transistor base terminals by way of said resistor divider networks.

Claim 3

The apparatus of claim 1 wherein said transistors are NPN junction transistors arranged to operate with quiescent collector currents of five microamperes.

Claim 4

The apparatus of claim 2 wherein said gain determining impedance members are resistors.

Claim 5

The apparatus of claim 3 further including a source of temperature-responsive bias signal coupled with the base terminals of said first and second feedback coupling transistors.

Claim 6

Low energy hybrid integrated circuit data acquisition apparatus for processing an analog data signal comprising the combination of: a first integrated circuit operational amplifier circuit having positive and negative input terminals and a unitary output terminal; first and second bipolar preamplifier transistors having base terminals connected to positive and negative data input terminals and collector terminals connected to said negative and positive first operational amplifier circuit input terminals respectively and having emitter terminals coupled with a pair of current source circuits; first and second bipolar feedback coupling transistors connected intermediate said preamplifier transistors and said current source circuits with collector terminals connected to said preamplifier transistor emitter terminals, emitter terminals connected to said current source circuits, and base terminals connected with an analog signal reference node and said first operational amplifier circuit output terminal respectively; a first, signal gain determining, impedance member connected between said preamplifier transistor emitter terminals; a second, feedback gain determining, impedance member connected between said feedback coupling transistor emitter terminals; a source of temperature dependent bias signal coupled with said base terminals of said feedback coupling transistors; a second integrated circuit operational amplifier sample and hold circuit having an output terminal, a first storage capacitor shunted by a first electronic switch and connected between said output and a negative input terminals thereof and having a positive input terminal connectable with said first operational amplifier circuit output terminal; a second electronic switch connected intermediate said first operational amplifier output terminal and said second operational amplifier positive input terminal; a second storage capacitor connected between said second operational amplifier positive input terminal and said analog reference node; driver circuit means for controlling the operation of said first and second electronic switches in response to a sample and discharge control signal; and an integrated circuit analog-to-digital converter circuit having an analog signal input terminal connectable with said second operational amplifier output terminal, a plurality of digital data bus connectable digital output terminals, an analog input reference terminal connected with said analog signal reference node and a digital reference terminal connectable with a digital data bus reference node and a plurality of control input terminals.

Claim 7

Low energy hybrid integrated circuit data acquisition apparatus for processing an analog data signal comprising the combination of: a first integrated circuit operational amplifier circuit having positive and negative input terminals and a unitary output terminal; first and second bipolar preamplifier transistors having base terminals connected to positive and negative data input terminals and collector terminals connected to said negative and positive first operational amplifier circuit input terminals respectively and having emitter terminals coupled with a pair of current source circuits; first and second bipolar feedback coupling transistors connected intermediate said preamplifier transistors and said current source circuits with collector terminals connected to said preamplifier transistor emitter terminals, emitter terminals connected to said current source circuits, and base terminals connected with an analog signal reference node and said first operational amplifier circuit output terminal respectively; a first, signal gain determining, impedance member connected between said preamplifier transistor emitter terminals; a second, feedback gain determining, impedance member connected between said feedback coupling transistor emitter terminals; a source of temperature dependent bias signal coupled with said base terminals of said feedback coupling transistors; a second integrated circuit operational amplifier sample and hold circuit having an output terminal, a first storage capacitor shunted by a first electronic switch and connected between said output and a negative input terminals thereof and having a positive input terminal connectable with said first operational amplifier circuit output terminal; a second electronic switch connected intermediate said first operational amplifier output terminal and said second operational amplifier positive input terminal; a second storage capacitor connected between said second operational amplifier positive input terminal and said analog reference node; driver circuit means for controlling the operation of said first and second electronic switches in response to a sample and discharge control signal; and an integrated circuit analog-to-digital converter circuit having an analog signal input terminal connectable with said second operational amplifier output terminal, a plurality of digital data bus connectable digital output terminals, an analog input reference terminal connected with said analog signal reference node and a digital reference terminal connectable with a digital data bus reference node and a plurality of control input terminals.

Claim 8

The data acquisition apparatus of claim 1 wherein said second operational amplifier sample and hold circuit further includes a connection with said source of temperature-dependent bias signal.

Claim 9

The data acquisition apparatus of claim 6 further including selectable means for connecting said second operational amplifier sample and hold circuit positive input terminal directly to said first operational amplifier circuit output terminal. whereby said data acquisition apparatus is capable of response to a slowly-varying signal received at said data input terminals without the functioning of said sample and hold circuit.

Claim 10

The data acquisition apparatus of claim 6 wherein said first and second preamplifier transistors and said first and second feedback coupling transistors each comprise characteristically matched pairs of transistors and further including means for maintaining the transistors in said pairs at the same temperature.

Claim 11

The data acquisition apparatus of claim 8 wherein said first and second electronic switches are comprised of field effect transistors.

Claim 12

The data acquisition apparatus of claim 9 wherein said data bus connectable digital output terminals of said analog-to-digital converter include the capability for attaining two binary output signal levels and an open circuit condition.

Claim 13

The data acquisition apparatus of claim 10 wherein said pair of current source circuits include first and second bipolar transistors of similar electrical and physical characteristics and similar temperature environment and wherein the base terminals of said transistors is connected to a temperature-responsive potential source.

Claim 14

The data acquisition apparatus of claim 11 wherein said temperature-responsive potential source includes a diode connected third bipolar transistor similar in characteristics and physical location to said first and second current source bipolar transistors.

Claim 15

The data acquisition of claim 12 wherein said first and second capacitors are equal in electrical size.

Claim 16

The data acquisition apparatus of claim 13 wherein said connection of said first and second feedback coupling transistors with said analog signal reference node and with said first operational amplifier circuit output terminal each include resistor dividing networks and wherein said resistor dividing networks have equal dividing ratios.